H8SSLASH2225 datasheet(287/1071 Pages) RENESAS

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H8S/2225 数据表(PDF) 287 Page - Renesas Technology Corp

部件名	H8S/2225

功能描述	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	1071 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

标志

287 / 1071 page

Section 7 Bus Controller

Rev. 5.00 Aug 08, 2006 page 201 of 982

REJ09B0054-0500

7.11

Resets and the Bus Controller

In a power-on reset, this LSI, including the bus controller, enters the reset state at that point, and

an executing bus cycle is discontinued.

In a manual reset, the bus controller's registers and internal state are maintained, and an executing

external bus cycle is completed. In this case,

WAIT input is ignored and write data is not

guaranteed.

When the DMAC* is initialized at the manual reset,

DACK and TEND output is disabled. The

DMAC* operates as I/O port controlled by DDR and DR.

Note: * Supported only by the H8S/2239 Group.

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