H8SSLASH2225 datasheet(283/1071 Pages) RENESAS

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Section 7 Bus Controller

Rev. 5.00 Aug 08, 2006 page 197 of 982

REJ09B0054-0500

7.9

Bus Release

This LSI can release the external bus in response to a bus request from an external device. In the

external bus released state, the internal bus master continues to operate as long as there is no

external access.

In external extended mode, the bus can be released to an external device by setting the BRLE bit

in BCRL to 1. Driving the

BREQ pin low issues an external bus request to this LSI. When the

BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus,

data bus, and bus control signals are placed in the high-impedance state, establishing the external

bus-released state.

In the external bus released state, an internal bus master can perform accesses using the internal

bus. When an internal bus master wants to make an external access, it temporarily defers

activation of the bus cycle, and waits for the bus request from the external bus master to be

dropped.

When the

BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the

external bus released state is terminated.

In the event of simultaneous external bus release request and external access request generation,

the order of priority is as follows:

(High) External bus release > Internal bus master external access (Low)

Table 7.5 shows pin states in the external bus released state.

Table 7.5

Pin States in Bus Released State

Pins

Pin State

A23 to A0

High impedance

D15 to D0

High impedance

CSn

High impedance

HWR

High impedance

LWR

High impedance

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