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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8S/2225 数据表(PDF) 302 Page - Renesas Technology Corp |
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H8S/2225 数据表(HTML) 302 Page - Renesas Technology Corp |
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302 / 1071 page  Section 8 DMA Controller (DMAC) Rev. 5.00 Aug 08, 2006 page 216 of 982 REJ09B0054-0500 Bit Bit Name Initial Value R/W Description 3 2 1 0 DTF3 DTF2 DTF1 DTF0 0 0 0 0 R/W R/W R/W R/W Data Transfer Factor 3 to 0 These bits select the data transfer factor (activation source). The factors that can be specified differ between normal mode and block transfer mode. Normal Mode 0000: Setting prohibited 0001: Setting prohibited 0010: Activated by DREQ pin falling edge input (detected as a low level in the first transfer after transfer is enabled) 0011: Activated by DREQ pin low-level input 010 ×: Setting prohibited 0110: Auto-request (cycle steal) 0111: Auto-request (burst) 1 ×××: Setting prohibited |
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