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数据搜索系统，热门电子元器件搜索 |
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H8/3003 数据表(PDF) 160 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 160 Page - Renesas Technology Corp |
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160 / 715 page  Bit 6—Compare Match Interrupt Enable (CMIE): Enables or disables the CMI interrupt requested when the CMF flag is set to 1 in RTMCSR. The CMIE bit is always cleared to 0 when PSRAME = 1 or DRAME = 1. Bit 6 CMIE Description 0 The CMI interrupt requested by CMF is disabled (Initial value) 1 The CMI interrupt requested by CMF is enabled Bits 5 to 3—Clock Select 2 to 0 (CKS2 to CKS0): These bits select an internal clock source for input to RTCNT. When used for refresh control, the refresh controller outputs a refresh request at periodic intervals determined by compare match between RTCNT and RTCOR. When used as an interval timer, the refresh controller generates CMI interrupts at periodic intervals determined by compare match. These bits are write-disabled when the PSRAME bit or DRAME bit is set to 1. Bit 5 Bit 4 Bit 3 CKS2 CKS1 CKS0 Description 0 0 0 Clock input is disabled (Initial value) 1 ø/2 clock source 1 0 ø/8 clock source 1 ø/32 clock source 1 0 0 ø/128 clock source 1 ø/512 clock source 1 0 ø/2048 clock source 1 ø/4096 clock source Bits 2 to 0—Reserved: Read-only bits, always read as 1. 142 |
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