H8SLASH3003 datasheet(162/715 Pages) RENESAS

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7.3 Operation

7.3.1 Area Division

One of three functions can be selected for the H8/3003 refresh controller: interfacing to DRAM

connected to area 3, interfacing to pseudo-static RAM connected to area 3, or interval timing.

Table 7-3 summarizes the register settings when these three functions are used.

Table 7-3 Refresh Controller Settings

Usage

DRAM Interface

PSRAM Interface

Interval Timer

RFSHCR

SRFMD

Selects self-refresh mode

Cleared to 0

PSRAME

Cleared to 0

Set to 1

Cleared to 0

DRAME

Set to 1

Cleared to 0

CAS/WE

Selects 2

CAS or

—

WE mode

M9/

Selects column

—

addressing mode

RFSHE

Selects

RFSH signal output

Cleared to 0

RCYCE

Selects insertion of refresh cycles

—

RTCOR

Refresh interval setting

Interrupt interval setting

RTMCSR

CKS2 to CKS0

CMF

Set to 1 when RTCNT = RTCOR

CMIE

Cleared to 0

Enables or disables

interrupt requests

P8DDR

P81DDR

Set to 1 (CS3 output)

Set to 0 or 1

ABWCR

ABW3

Cleared to 0

—

DRAM Interface: To set up area 3 for connection to 16-bit-wide DRAM, initialize RTCOR,

RTMCSR, and RFSHCR in that order, clearing bit PSRAME to 0 and setting bit DRAME to 1.

Set bit P81DDR to 1 in the port 8 data direction register (P8DDR) to enable CS3 output. In

ABWCR, make area 3 a 16-bit-access area.

Pseudo-Static RAM Interface: To set up area 3 for connection to pseudo-static RAM, initialize

RTCOR, RTMCSR, and RFSHCR in that order, setting bit PSRAME to 1 and clearing bit

DRAME to 0. Set bit P81DDR to 1 in P8DDR to enable CS3 output.

144

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