H8SLASH3003 datasheet(164/715 Pages) RENESAS

164 / 715 page

Table 7-4 Area 3 Settings, DRAM Access Cycles, and Refresh Cycles

Area 3 Settings

Read/Write Cycle by CPU or DMAC

Refresh Cycle

2-state-access area

• 3 states

(AST3 = 0)

• Wait states cannot be inserted

3-state-access area

• 3 states

(AST3 = 1)

• Wait states can be inserted

To insert refresh cycles, set the RCYCE bit to 1 in RFSHCR. Figure 7-3 shows the state

transitions for execution of refresh cycles.

When the first refresh request occurs after exit from the reset state or standby mode, the refresh

controller does not execute a refresh cycle, but goes into the refresh request pending state. Note

this point when using a DRAM that requires a refresh cycle for initialization.

When a refresh request occurs in the refresh request pending state, the refresh controller acquires

the bus right, then executes a refresh cycle. If another refresh request occurs during execution of

the refresh cycle, it is ignored.

Figure 7-3 State Transitions for Refresh Cycle Execution

Refresh

request*

Refresh

request*

Exit from reset or standby mode

Refresh request pending state

Requesting bus right

Executing refresh cycle

Refresh request

Bus granted

End of refresh

cycle

Note:

A refresh request is ignored if it occurs while the refresh controller is requesting the

bus right or executing a refresh cycle.

146

H8/3003 数据表(PDF) 164 Page - Renesas Technology Corp

H8/3003 数据表(HTML) 164 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载