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H8/3003 数据表(PDF) 163 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 163 Page - Renesas Technology Corp |
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163 / 715 page  Interval Timer: When PSRAME = 0 and DRAME = 0, the refresh controller operates as an interval timer. After setting RTCOR, select an input clock in RTMCSR and set the CMIE bit to 1. CMI interrupts will be requested at compare match intervals determined by RTCOR and bits CKS2 to CKS0 in RTMCSR. When setting RTCOR, RTMCSR, and RFSHCR, make sure that PSRAME = 0 and DRAME = 0. Writing is disabled when either of these bits is set to 1. 7.3.2 DRAM Refresh Control Refresh Request Interval and Refresh Cycle Execution: The refresh request interval is determined by the settings of RTCOR and bits CKS2 to CKS0 in RTMCSR. Figure 7-2 illustrates the refresh request interval. Figure 7-2 Refresh Request Interval (RCYCE = 1) Refresh requests are generated at regular intervals as shown in figure 7-2, but the refresh cycle is not actually executed until the refresh controller gets the bus right. Table 7-4 summarizes the relationship among area 3 settings, DRAM read/write cycles, and refresh cycles. RTCOR H'00 RTCNT Refresh request 145 |
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