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H5GQ1H24AFR-R0C 数据表(PDF) 119 Page - Hynix Semiconductor |
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H5GQ1H24AFR-R0C 数据表(HTML) 119 Page - Hynix Semiconductor |
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119 / 173 page ![]() This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 119 H5GQ1H24AFR 5.22. TEMPERATURE SENSOR GDDR5 SGRAMs incorporate a temperature sensor with digital temperature readout function. This func‐ tion allows the controller to monitor the GDDR5 SGRAM die’s junction temperature and use this informa‐ tion to make sure the device is operated within the specified temperature range or to adjust interface timings relative to temperature changes over time. The temperature sensor is enabled by bit A6 in Mode Register 7 (MR7). In this case the temperature read‐ out is valid after tTSEN. Hynix applies 10us to tTSEN. The temperature readout uses the DRAM Info mode feature. The digital value is driven asynchronously on the DQ bus following the MRS command to Mode Register 3 (MR3) that sets bit A7 to 1 and bit A6 to 0. The temperature readout will be continuously driven until an MRS command sets both bits to 0. The GDDR5 SGRAM’s junction temperature is linearly encoded as shown in Table 35. Hynix has the read‐ out to a subset of six digital codes out of Table 35, corresponding to six temperature thresholds. Table 34 Temperature Sensor Readout Pattern Temperature [°C] Binary Temperature Readout MF=0: MF=1: DQ[5:0] DQ[31:26] < 45 000000 55 000001 65 000011 75 000111 85 001111 95 011111 > 95 111111 |
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