H5GQ1H24AFR-R0C datasheet(120/173 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

120

H5GQ1H24AFR

5.23. DUTY CYCLE CORRECTOR (DCC)

As GDDR5 SGRAMs can operate with the PLL off during normal operation, the use of a Duty Cycle Cor‐

rector (DCC) can correct for the duty cycle of the WCK. DCC can be used at any time, however, rising and

falling edges of WCK can be shifted according to the DCC type. The DCC should be enabled before WCK

training and should be run for tDCC in order to effectively correct any error.

DCC can correct the duty cycle error within the range of ± 100ps.

Figure 77. Timing Diagram of DCC Control Signals

DCC control signals

•DCC reset : The DCC reset is used to initialize the DCC code and should be issued anytime before the WCK

enables (MRS7 A11:1, A10:0)

•DCC start : The DCC start is used to update the DCC code and should be issued anytime after the WCK is stable

(MRS7 A11:0, A10:1)

•DCC stop : The DCC stop is used to make it stop to update the DCC code while the DCC code is held. This should

be issued after enough time from DCC start if needs (MRS7 A11:0, A10:0)

Table 35 DCC Timings

Parameter

Symbol

Min

Max

Unit

Required time for duty cycle corrector

tDCC

150

‐

tCK

Training

PLL Reset

DCC start

DCC stop or not

DCC reset

Enter WCK2CK

Training (reset WCK

divide by circuits)

Enter WCK2CK

Training (sets data

synchronizers, resets

FIFO pointers)

WCK#

WCK

CK#

CMD

NOP

MRS

NOP

MRS

NOP

MRS

A.C.

tWCKTMRS

tMRD

tWCKTTR

tDCC

tLK

tMRD

Start WCK2CK Phase

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