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H5GQ1H24AFR-R0C 数据表(PDF) 139 Page - Hynix Semiconductor |
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H5GQ1H24AFR-R0C 数据表(HTML) 139 Page - Hynix Semiconductor |
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139 / 173 page  Rev. 1.0 /Nov. 2009 139 H5GQ1H24AFR PARAMETER a, b SYMBOL 5.0Gbps 4.5Gbps UNIT NOTES MIN MAX MIN MAX LDFF to LDFF command cycle time tLTLTR 4 - 4 - tCK LDFF(111) to LDFF command cycle time tLTL7TR 4 - 4 - tCK ao LDFF(111) to RDTR command cycle delay tLTRTR 4 - 4 - tCK READ or RDTR to LDFF command delay tRDTLT 4 - 4 - tCK WRITE to LDFF command delay tWRTLT WL+5 - WL+5 - tCK WRTR to RDTR command delay tWTRTR WL- tWLmin - WL- tWLmin -tCK WRITE to WRTR command delay tWRWTR WL+tCR CWL+2 - WL+tCR CWL+2 -tCK Internal WRITE to READ command delay same bank group tWTRL 5 - 5 - ns af Internal WRITE to READ command delay different bank groups tWTRS 5 - 5 - ns ag READ or RDTR to WRITE or WRTR command delay tRTW [CLmrs+(BL /4)+2- WLmrs]*tC K - [CLmrs+(BL /4)+2- WLmrs]*tC K -tCK ap Write Latency tWL 3 7 3 7 tCK aq Power-Down and Refresh Timings CKE# min high and low pulse width tCKE 12 - 11 - tCK Valid CK Clock required after self refresh entry tCKSRE 12 - 11 - tCK Valid CK Clock required before self refresh exit tCKSRX 12 - 11 - tCK READ to SELF REFRESH ENTRY or POWER DOWN ENTRY command delay tRDSRE CL+2tCK - CL+2tCK - tCK ar WRITE to SELF REFRESH ENTRY or POWER DOWN ENTRY command delay tWRSRE TBD-TBD- tCK as REFRESH command period tRFC 65 - 65 - ns Exit self refresh to non-READ/WRITE command delay tXSNRW tRFC - tRFC - ns Exit self refresh to READ/WRITE command delay tXSRW tRFC+ tRCD - tRFC+ tRCD -tCK at Refresh period tREF - 32 - 32 ms Average periodic refresh interval 8k rows tREFI - 3.9 - 3.9 us au 16k rows - 1.9 - 1.9 Min Power down entry to exit time tPD 12 11 tCK Table 44. AC Timings (@1.5V) |
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