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H5GQ1H24AFR-R0C 数据表(PDF) 141 Page - Hynix Semiconductor |
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H5GQ1H24AFR-R0C 数据表(HTML) 141 Page - Hynix Semiconductor |
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141 / 173 page  Rev. 1.0 /Nov. 2009 141 H5GQ1H24AFR PARAMETER a, b SYMBOL 4.0Gbps - UNIT NOTES MIN MAX MIN MAX CK and WCK Timings CK Clock cycle time PLL on tCK 12 ns PLL off 1 20 CK Clock high-level width tCH 0.470 0.530 tCK C CK Clock low-level width tCL 0.470 0.530 tCK C Min CK Clock half period tHP 0.470 - tCK Max CK Clock frequency with bank groups disabled fCKBG - 1000 MHz d Max CK Clock frequency with bank groups enabled and tCCDL=3tCK fCKBG4 - 1000 MHz d Max CK Clock frequency with WCK2CK alignment at pins fCKPIN - 1000 MHz e Max CK Clock frequency in RDQS Mode fCKRDQS - TBD MHz f Max CK Clock frequency for device operation with VREFD2 fCKVREFD2 - TBD MHz g Max CK Clock frequency for WCK-to-CK auto synchronization in WCK2CK training mode fCKAUTOSYNC - 100 MHz h Max CK Clock frequency for device operation with Low Frequency Mode enabled fCKLF - 800 MHz i WCK Clock cycle time PLL on tWCK 0.5 1 ns j PLL off 0.5 10 WCK Clock high-level width tWCKH 0.470 0.530 tWCK k,l WCK Clock low-level width tWCKL 0.470 0.530 tWCK k,l Min WCK Clock half period tWCKHP 0.470 - tWCK Command and Address Input Timings Command input setup time tCMDS 0.25 - ns m,n Command input hold time tCMDH 0.25 - ns m,n Command input pulse width tCMDPW 0.7 - ns m,n,o Address input setup time tAS 0.125 - ns m,n,p Address input hold time tAH 0.125 - ns m,n,p Address input pulse width tAPW 0.45 - ns m,n,o,p Table 44. AC Timings (@1.5V) |
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