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H5GQ1H24AFR-R0C 数据表(PDF) 145 Page - Hynix Semiconductor |
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H5GQ1H24AFR-R0C 数据表(HTML) 145 Page - Hynix Semiconductor |
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145 / 173 page  Rev. 1.0 /Nov. 2009 145 H5GQ1H24AFR PARAMETER a, b SYMBOL 4.0Gbps - UNIT NOTES MIN MAX MIN MAX NOP/DESELECT commands required upon power- down and self refresh entry tCPDED 2 - tCK Power down exit time tXPN 10 - tCK Miscellaneous Timings MODE REGISTER SET command period tMRD 4 - tCK PLL enabled to PLL lock delay tLK - 5000 tCK PLL standby time tSTDBTY - TBD us ax DVS voltage stabilization time tVS TBD - us REFRESH to calibration update complete delay tKO - 40 ns Active termination setup time tATS 10 - ns Active termination hold time tATH 10 - ns READ to data out delay in address training mode tADR 0.5*tCK+ 0 0.5*tCK+ 10 tCK q Address training exit to DQ in ODT state delay tADZ - 0.5*tCK+ 10 ns Vendor ID on tWRIDON - 11 ns Venodr ID off tWRIDOFF - 11 ns Temperature sensor enable delay tTSEN 10 - us Table 44. AC Timings (@1.5V) |
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