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H5GQ1H24AFR-R0C 数据表(PDF) 143 Page - Hynix Semiconductor |
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H5GQ1H24AFR-R0C 数据表(HTML) 143 Page - Hynix Semiconductor |
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143 / 173 page  Rev. 1.0 /Nov. 2009 143 H5GQ1H24AFR PARAMETER a, b SYMBOL 4.0Gbps - UNIT NOTES MIN MAX MIN MAX DQ/DBI# data input valid window PLL on tDIVW 0.15 - ns y,z,ab PLL off 0.15 - DQ/DBI# input skew within double byte tDQDQI -0.1 0.1 ns ac DQ/DBI#/EDC output skew within double byte tDQDQO -0.125 0.125 ns ad Row Access Timings Active to Active command period tRC 40 - ns Active to PRECHARGE command period tRAS 28 9*tREFI ns ae Active to READ command delay tRCDRD 12 - ns Active to WRITE command delay tRCDWR 10 - ns Active to RDTR command delay tRCDRTR 10 - ns Active to WRTR command delay tRCDWTR 10 - ns Active to LDFF command delay tRCDLTR 10 - ns REFRESH to RDTR or WRTR command delay tREFTR 10 - ns Active bank A to Active bank B command delay same bank group tRRDL 5.5 - ns af Active bank A to Active bank B command delay different bank groups tRRDS 5.5 - ns ag Four bank activate window tFAW 23 - ns ah Thirty two bank activate window t32AW 184 - ns ai READ to PRECHARGE command delay same bank with bank groups enabled tRTPL 2 - tCK aj READ to PRECHARGE command delay same bank with bank groups disabled tRTPS 2 - tCK ak PRECHARGE to PRECHARGE command delay tPPD 1 - ns PRECHARGE command period tRP 12 - ns WRITE recovery time tWR 12 - ns Auto precharge write recovery + precharge time tDAL 24 - tCK al Column Access Timings RD/WR bank A to RD/WR bank B command delay same bank group tCCDL 3 - tCK af,am RD/WR bank A to RD/WR bank B command delay different bank groups tCCDS 2 - tCK ag,an Table 44. AC Timings (@1.5V) |
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