910GL datasheet(131/426 Pages) INTEL

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Host-PCI Express* Bridge Registers (D1:F0)

(Intel® 82915G/82915P/82915PL Only)

Datasheet

131

Bit

Access &

Default

Description

Received Target Abort Status (RTAS): Hardwired to 0. The concept of a target

abort does not exist on primary side of this device.

Signaled Target Abort Status (STAS): Hardwired to 0. The concept of a target

abort does not exist on primary side of this device.

10:9

00b

DEVSELB Timing (DEVT): This device is not the subtractive decoded device on

bus 0. This bit field is therefore hardwired to 00b to indicate that the device uses

the fastest possible decode.

Master Data Parity Error (PMDPE): Because the primary side of the PCI

Express* x16 Graphics Interface’s virtual PCI-to-PCI bridge is integrated with the

(G)MCH functionality, there is no scenario where this bit will get set. Because

hardware will never set this bit, it is impossible for software to have an

opportunity to clear this bit or otherwise test that it is implemented. The PCI

specification defines it as a R/WC; however, for this implementation, an RO

definition behaves the same way and will meet all Microsoft testing requirements.

This bit can only be set when the Parity Error Enable bit in the PCI Command

Fast Back-to-Back (FB2B): Hardwired to 0.

Reserved

66/60MHz capability (CAP66): Hardwired to 0.

Capabilities List: This bit indicates that a capabilities list is present. Hardwired

to 1.

INTA Status: This field indicates that an interrupt message is pending internally

to the device. Only PME and Hot Plug sources feed into this status bit (not PCI

INTA-INTD assert and de-assert messages). The INTA Assertion Disable bit,

PCICMD1[10], has no effect on this bit.

2:0

Reserved

910GL 数据表(PDF) 131 Page - Intel Corporation

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