ADSP-BF504 datasheet(31/80 Pages) AD

31 / 80 page

Preliminary Technical Data

Rev. PrC

Page 31 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

PROCESSOR — TIMING SPECIFICATIONS

Clock and Reset Timing

Table 23 and Figure 10 describe clock and reset operations. Per

the CCLK and SCLK timing specifications in Table 14 to

Table 16, combinations of CLKIN and clock multipliers must

not select core/peripheral clocks in excess of the processor’s

speed grade.

Table 23. Clock and Reset Timing

Parameter

Min

Max

Unit

Timing Requirements

fCKIN

CLKIN Frequency1, 2, 3, 4

MHz

tCKINL

CLKIN Low Pulse1

tCKINH

CLKIN High Pulse1

tWRST

RESET Asserted Pulse Width Low

11 × tCKIN

Switching Characteristic

tBUFDLAY

CLKIN to CLKBUF Delay

1 Applies to PLL bypass mode and PLL non bypass mode.

2 Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed f

VCO, fCCLK, and fSCLK settings discussed in Table 14 on Page 26 through

Table 16 on Page 26.

3 The t

CKIN period (see Figure 10) equals 1/fCKIN.

4 If the DF bit in the PLL_CTL register is set, the minimum fCKIN specification is 24 MHz.

5 Applies after power-up sequence is complete. See Table 24 and Figure 11 for power-up reset timing.

Figure 10. Clock and Reset Timing

CLKIN

tWRST

tCKIN

tCKINL

tCKINH

tBUFDLAY

RESET

CLKBUF

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