ADSP-BF504 datasheet(5/80 Pages) AD

5 / 80 page

Preliminary Technical Data

Rev. PrC

Page 5 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

Blackfin processors support a modified Harvard architecture in

combination with a hierarchical memory structure. Level 1 (L1)

memories are those that typically operate at the full processor

speed with little or no latency. At the L1 level, the instruction

memory holds instructions only. The data memory holds data,

and a dedicated scratchpad data memory stores stack and local

variable information.

In addition, multiple L1 memory blocks are provided, offering a

configurable mix of SRAM and cache. The memory manage-

ment unit (MMU) provides memory protection for individual

tasks that may be operating on the core and can protect system

registers from unintended access.

The architecture provides three modes of operation: user mode,

supervisor mode, and emulation mode. User mode has

restricted access to certain system resources, thus providing a

protected software environment, while supervisor mode has

unrestricted access to the system and core resources.

The Blackfin processor instruction set has been optimized so

that 16-bit opcodes represent the most frequently used instruc-

tions, resulting in excellent compiled code density. Complex

DSP instructions are encoded into 32-bit opcodes, representing

fully featured multifunction instructions. Blackfin processors

support a limited multi-issue capability, where a 32-bit instruc-

tion can be issued in parallel with two 16-bit instructions,

allowing the programmer to use many of the core resources in a

single instruction cycle.

The Blackfin processor assembly language uses an algebraic syn-

tax for ease of coding and readability. The architecture has been

optimized for use in conjunction with the C/C++ compiler,

resulting in fast and efficient software implementations.

MEMORY ARCHITECTURE

The Blackfin processor views memory as a single unified

4G byte address space, using 32-bit addresses. All resources,

including internal memory, external memory, and I/O control

registers, occupy separate sections of this common address

space. The memory portions of this address space are arranged

in a hierarchical structure to provide a good cost/performance

balance of some very fast, low-latency core-accessible memory

as cache or SRAM, and larger, lower-cost and performance

interface-accessible memory systems. See Figure 3.

The core-accessible L1 memory system is the highest-perfor-

mance memory available to the Blackfin processor. The

interface-accessible memory system, accessed through the

external bus interface unit (EBIU), provides access to the inter-

nal flash memory and boot ROM.

The memory DMA controller provides high-bandwidth data-

movement capability. It can perform block transfers of code or

data between the internal memory and the external

memory spaces.

Internal (Core-Accessible) Memory

The processor has three blocks of core-accessible memory, pro-

viding high-bandwidth access to the core.

The first block is the L1 instruction memory, consisting of

32K bytes SRAM, of which 16K bytes can be configured as a

four-way set-associative cache. This memory is accessed at full

processor speed.

The second core-accessible memory block is the L1 data mem-

ory, consisting of 32K bytes of SRAM, of which 16K bytes may

be configured as cache. This memory block is accessed at full

processor speed.

The third memory block is 4K bytes of scratchpad SRAM which

runs at the same speed as the L1 memories, but is only accessible

as data SRAM and cannot be configured as cache memory.

External (Interface-Accessible) Memory

External memory is accessed via the EBIU memory port. This

16-bit interface provides a glueless connection to the internal

flash memory and boot ROM. Internal flash memory ships from

the factory in an erased state except for block 0 of the parameter

bank. Block 0 of the Flash memory parameter bank ships from

the factory in an unknown state. An erase operation should be

performed prior to programming this block.

I/O Memory Space

The processor does not define a separate I/O space. All

resources are mapped through the flat 32-bit address space. On-

chip I/O devices have their control registers mapped into mem-

ory-mapped registers (MMRs) at addresses near the top of the

4G byte address space. These are separated into two smaller

blocks, one which contains the control MMRs for all core func-

tions, and the other which contains the registers needed for

setup and control of the on-chip peripherals outside of the core.

The MMRs are accessible only in supervisor and emulation

modes and appear as reserved space to on-chip peripherals.

Figure 3. Internal/External Memory Map

0x0000 0000

0x2000 0000

0x2040 0000

0xEF00 0000

0xEF00 1000

0xFF80 0000

0xFF80 4000

0xFF80 8000

0xFFA0 0000

0xFFA0 4000

0xFFA0 8000

0xFFA1 4000

0xFFB0 0000

0xFFB0 1000

0xFFC0 0000

0xFFE0 0000

0xFFFF FFFF

SYNC FLASH (32M BITS) *

RESERVED

BOOT ROM (4K BYTES)

L1 DATA BANK A SRAM (16K BYTES)

RESERVED

L1 DATA BANK A SRAM/CACHE (16K BYTES)

RESERVED

L1 INSTRUCTION SRAM/CACHE (16K BYTES)

RESERVED

L1 INSTRUCTION BANK A SRAM (16K BYTES)

RESERVED

INTERNAL SCRATCHPAD RAM (4K BYTES)

RESERVED

SYSTEM MEMORY MAPPED REGISTERS

CORE MEMORY MAPPED REGISTERS

* AVAILABLE ON PARTS WITH SYNC FLASH (F)

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