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ADSP-BF504 数据表(PDF) 1 Page - Analog Devices |
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ADSP-BF504 数据表(HTML) 1 Page - Analog Devices |
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1 / 80 page  Preliminary Technical Data Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Blackfin Embedded Processor ADSP-BF504/F,ADSP-BF506F Rev. PrC Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2010 Analog Devices, Inc. All rights reserved. FEATURES Up to 400 MHz high-performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of programming and compiler-friendly support Advanced debug, trace, and performance monitoring Accepts a range of supply voltages for internal and I/O opera- tions. See Processor — Operating Conditions on Page 25 Internal 32M bit flash (available on ADSP-BF504F and ADSP-BF506F processors) Internal ADC (available on ADSP-BF506F processor) Off-chip voltage regulator interface 88-lead (12 mm × 12 mm) LFCSP package for ADSP-BF504 and ADSP-BF504F processors 120-lead (14 mm × 14 mm) LQFP package for ADSP-BF506F processor MEMORY 68K bytes of L1 SRAM (processor core-accessible) memory: (See Table 1 on Page 3 for L1 and L3 memory size details) External (interface-accessible) memory controller with glue- less support for internal 32M bit flash and boot ROM Flexible booting options from internal flash and SPI memory or from host devices including SPI, PPI, and UART Memory management unit providing memory protection PERIPHERALS Two 32-bit up/down counters with rotary support Eight 32-bit timers/counters with PWM support Two three-phase 16-bit center-based PWM units Two dual-channel, full-duplex synchronous serial ports (SPORTs), supporting eight stereo I2S channels Two Serial Peripheral Interface (SPI) compatible ports Two UARTs with IrDA ® support Parallel peripheral interface (PPI), supporting ITU-R 656 video data formats Removable storage interface (RSI) controller for MMC, SD, SDIO, and CE-ATA Internal ADC with 12 channels, 12 bits, and up to 2 MSPS ADC controller module (ACM), providing a glue-less interface between Blackfin processor and internal or external ADC Controller Area Network (CAN) controller Two-wire interface (TWI) controller 12 peripheral DMAs Two memory-to-memory DMA channels Event handler with 52 interrupt inputs 35 general-purpose I/Os (GPIOs), with programmable hysteresis Debug/JTAG interface On-chip PLL capable of frequency multiplication Figure 1. Processor Block Diagram SPORT1–0 VOLTAGE REGULATOR INTERFACE GPIO PORT F PORT G PORT H JTAG TEST AND EMULATION PERIPHERAL ACCESS BUS PWM 1–0 WATCHDOG TIMER SPI1–0 RSI ACM PPI CAN COUNTER1–0 TWI BOOT ROM DMA ACCESS BUS INTERRUPT CONTROLLER DMA CONTROLLER L1 DATA MEMORY L1 INSTRUCTION MEMORY 16 DCB EAB MEMORY PORT FLASH CONTROL B UART1–0 DEB 32M BIT FLASH TIMER7–0 ADC |
类似零件编号 - ADSP-BF504 |
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类似说明 - ADSP-BF504 |
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