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ADSP-BF504 数据表(PDF) 7 Page - Analog Devices

部件名 ADSP-BF504
功能描述  Blackfin Embedded Processor
PDF  80 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADSP-BF504 数据表(HTML) 7 Page - Analog Devices

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Preliminary Technical Data
Rev. PrC
|
Page 7 of 80
|
January 2010
ADSP-BF504/F,ADSP-BF506F
Table 3. System Interrupt Controller (SIC)
Peripheral Interrupt Source
General Purpose
Interrupt (at Reset)
Peripheral Interrupt ID
Default Core
Interrupt ID
SIC Registers
PLL Wakeup Interrupt
IVG7
0
0
IAR0
IMASK0, ISR0, IWR0
DMA Error (generic)
IVG7
1
0
IAR0
IMASK0, ISR0, IWR0
PPI Status
IVG7
2
0
IAR0
IMASK0, ISR0, IWR0
SPORT0 Status
IVG7
3
0
IAR0
IMASK0, ISR0, IWR0
SPORT1 Status
IVG7
4
0
IAR0
IMASK0, ISR0, IWR0
UART0 Status
IVG7
5
0
IAR0
IMASK0, ISR0, IWR0
UART1 Status
IVG7
6
0
IAR0
IMASK0, ISR0, IWR0
SPI0 Status
IVG7
7
0
IAR0
IMASK0, ISR0, IWR0
SPI1 Status
IVG7
8
0
IAR1
IMASK0, ISR0, IWR0
CAN Status
IVG7
9
0
IAR1
IMASK0, ISR0, IWR0
RSI Mask 0 Interrupt
IVG7
10
0
IAR1
IMASK0, ISR0, IWR0
Reserved
–
11
–
IAR1
IMASK0, ISR0, IWR0
CNT0 Interrupt
IVG8
12
1
IAR1
IMASK0, ISR0, IWR0
CNT1 Interrupt
IVG8
13
1
IAR1
IMASK0, ISR0, IWR0
DMA Channel 0 (PPI Rx/Tx)
IVG9
14
2
IAR1
IMASK0, ISR0, IWR0
DMA Channel 1 (RSI Rx/Tx)
IVG9
15
2
IAR1
IMASK0, ISR0, IWR0
DMA Channel 2 (SPORT0 Rx)
IVG9
16
2
IAR2
IMASK0, ISR0, IWR0
DMA Channel 3 (SPORT0 Tx)
IVG9
17
2
IAR2
IMASK0, ISR0, IWR0
DMA Channel 4 (SPORT1 Rx)
IVG9
18
2
IAR2
IMASK0, ISR0, IWR0
DMA Channel 5 (SPORT1 Tx)
IVG9
19
2
IAR2
IMASK0, ISR0, IWR0
DMA Channel 6 (SPI0 Rx/Tx)
IVG10
20
3
IAR2
IMASK0, ISR0, IWR0
DMA Channel 7 (SPI1 Rx/Tx)
IVG10
21
3
IAR2
IMASK0, ISR0, IWR0
DMA Channel 8 (UART0 Rx)
IVG10
22
3
IAR2
IMASK0, ISR0, IWR0
DMA Channel 9 (UART0 Tx)
IVG10
23
3
IAR2
IMASK0, ISR0, IWR0
DMA Channel 10 (UART1 Rx)
IVG10
24
3
IAR3
IMASK0, ISR0, IWR0
DMA Channel 11 (UART1 Tx)
IVG10
25
3
IAR3
IMASK0, ISR0, IWR0
CAN Receive
IVG11
26
4
IAR3
IMASK0, ISR0, IWR0
CAN Transmit
IVG11
27
4
IAR3
IMASK0, ISR0, IWR0
TWI
IVG11
28
4
IAR3
IMASK0, ISR0, IWR0
Port F Interrupt A
IVG11
29
4
IAR3
IMASK0, ISR0, IWR0
Port F Interrupt B
IVG11
30
4
IAR3
IMASK0, ISR0, IWR0
Reserved
–
31
–
IAR3
IMASK0, ISR0, IWR0
Timer 0
IVG12
32
5
IAR4
IMASK1, ISR1, IWR1
Timer 1
IVG12
33
5
IAR4
IMASK1, ISR1, IWR1
Timer 2
IVG12
34
5
IAR4
IMASK1, ISR1, IWR1
Timer 3
IVG12
35
5
IAR4
IMASK1, ISR1, IWR1
Timer 4
IVG12
36
5
IAR4
IMASK1, ISR1, IWR1
Timer 5
IVG12
37
5
IAR4
IMASK1, ISR1, IWR1
Timer 6
IVG12
38
5
IAR4
IMASK1, ISR1, IWR1
Timer 7
IVG12
39
5
IAR4
IMASK1, ISR1, IWR1
Port G Interrupt A
IVG12
40
5
IAR5
IMASK1, ISR1, IWR1



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