ADSP-BF504 datasheet(16/80 Pages) AD

16 / 80 page

Rev. PrC

Page 16 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

Preliminary Technical Data

All on-chip peripherals are clocked by the system clock (SCLK).

The system clock frequency is programmable by means of the

SSEL3–0 bits of the PLL_DIV register. The values programmed

into the SSEL fields define a divide ratio between the PLL output

(VCO) and the system clock. SCLK divider values are 1 through

15. Table 6 illustrates typical system clock ratios.

Note that the divisor ratio must be chosen to limit the system

clock frequency to its maximum of fSCLK. The SSEL value can be

changed dynamically without any PLL lock latencies by writing

the appropriate values to the PLL divisor register (PLL_DIV).

The core clock (CCLK) frequency can also be dynamically

changed by means of the CSEL1–0 bits of the PLL_DIV register.

Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in

Table 7. This programmable core clock capability is useful for

fast core frequency modifications.

The maximum CCLK frequency both depends on the part’s

speed grade (see Page 79) and depends on the applied VDDINT

voltage. See Table 14 for details. The maximal system clock rate

(SCLK) depends on the applied VDDINT and VDDEXT voltages (see

Table 16).

BOOTING MODES

The processor has several mechanisms (listed in Table 8) for

automatically loading internal and external memory after a

reset. The boot mode is defined by the BMODE input pins dedi-

cated to this purpose. There are two categories of boot modes.

In master boot modes, the processor actively loads data from

parallel or serial memories. In slave boot modes, the processor

receives data from external host devices.

The boot modes listed in Table 8 provide a number of mecha-

nisms for automatically loading the processor’s internal and

external memories after a reset. By default, all boot modes use

the slowest meaningful configuration settings. Default settings

can be altered via the initialization code feature at boot time.

Some boot modes require a boot host wait (HWAIT) signal,

which is a GPIO output signal that is driven and toggled by the

boot kernel at boot time. If pulled high through an external pull-

up resistor, the HWAIT signal behaves active high and will be

driven low when the processor is ready for data. Conversely,

when pulled low, HWAIT is driven high when the processor is

ready for data. When the boot sequence completes, the HWAIT

pin can be used for other purposes. The BMODE pins of the

reset configuration register, sampled during power-on resets

and software-initiated resets, implement the modes shown in

Table 8.

• IDLE State / No Boot (BMODE = 0x0) — In this mode, the

boot kernel transitions the processor into Idle state. The

processor can then be controlled through JTAG for recov-

ery, debug, or other functions.

• Boot from stacked parallel flash in 16-bit asynchronous

mode (BMODE = 0x1) — In this mode, the boot kernel

starts booting from address 0x2000 0000.

• Boot from stacked parallel flash in 16-bit synchronous

mode (BMODE = 0x2) — In this mode, the boot kernel

loads the first block header from address 0x2000 0000. Boot

kernel operation from this point is TBD.

• Boot from serial SPI memory, EEPROM or flash

(BMODE = 0x3) — 8-, 16-, 24-, or 32-bit addressable

devices are supported. The processor uses the PF13 GPIO

pin to select a single SPI EEPROM/flash device (connected

to the SPI0 interface) and submits a read command and

successive address bytes (0x00) until a valid 8-, 16-, 24-, or

Figure 5. Frequency Modification Methods

Table 6. Example System Clock Ratios

Signal Name

SSEL3–0

Divider Ratio

VCO/SCLK

Example Frequency Ratios

(MHz)

VCO

SCLK

0001

1:1

0110

6:1

300

1010

10:1

400

Table 7. Core Clock Ratios

Signal Name

CSEL1–0

Divider Ratio

VCO/CCLK

Example Frequency Ratios

(MHz)

VCO

CCLK

1:1

300

2:1

300

150

4:1

400

100

8:1

200

PLL

0.5 to 64

÷1 to 15

÷1, 2, 4, 8

VCO

CLKIN

“FINE” ADJUSTMENT

REQUIRES PLL SEQUENCING

“COARSE” ADJUSTMENT

ON-THE-FLY

CCLK

SCLK

CCLK

Table 8. Booting Modes

BMODE2–0 Description

000

Idle/No Boot

001

Boot from internal parallel flash in async mode1

1 This boot mode supported on ADSP-BF504F and ADSP-BF506F processor only.

010

Boot from internal parallel flash in sync mode1

011

Boot through SPI0 master from SPI memory

100

Boot through SPI0 slave from host device

101

Boot through PPI from host

110

Reserved

111

Boot through UART0 slave from host device

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