ADSP-BF504 datasheet(22/80 Pages) AD

22 / 80 page

Rev. PrC

Page 22 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

Preliminary Technical Data

PG14/UA0_RTS/SD_D6/TMR0/PPI_FS1/CUD1

I/O GPIO/ UART0 RTS/ SD Data 6 /Timer0 / PPI FS1 / Count Up Dir 1

TBD

PG15/UA0_CTS/SD_D7/TMR1/PPI_FS2/CDG1

I/O GPIO/ UART0 CTS / SD Data 7 /Timer1 /PPI FS2 /Count Down Dir 1

TBD

Port H: GPIO and Multiplexed Peripherals

PH0/ACM_A2/DT1PRI/SPI0_SEL3/WAKEUP

I/O GPIO /ADC CM A2/SPORT1 TX Pri Data/SPI0 Slave Select 3 /Wake-up Input

TBD

PH1/ACM_A1/TFS1/SPI1_SEL3/TACLK3

I/O GPIO/ADC CM A1/SPORT1 TX Frame Sync/SPI1 Slave Select 3/Alt Timer CLK 3

TBD

PH2/ACM_A0/TSCLK1/SPI1_SEL2/TACI7

I/O GPIO/ ADC CM A0/ SPORT1 TX Serial CLK /SPI1 Slave Select 2/ Alt Capture In 7

TBD

TWI (Two-Wire Interface) Port

SCL

I/O

TWI Serial Clock (This signal is an open-drain output and requires a pull-up

resistor. Consult version 2.1 of the I2C specification for the proper resistor

value.)

TBD

SDA

I/O

TWI Serial Data (This signal is an open-drain output and requires a pull-up

resistor. Consult version 2.1 of the I

2C specification for the proper resistor

value.)

TBD

JTAG Port

TCK

JTAG CLK

TDO

JTAG Serial Data Out

TDI

JTAG Serial Data In

TMS

JTAG Mode Select

TRST

JTAG Reset

(This signal should be pulled low if the JTAG port is not used.)

EMU

Emulation Output

Clock

CLKIN

CLK/Crystal In

XTAL

Crystal Output

EXTCLK

Clock Output

Mode Controls

RESET

IReset

NMI

Nonmaskable Interrupt

(This signal should be pulled high when not used.)

BMODE2–0

Boot Mode Strap 2-0

ADSP-BF50x Voltage Regulation I/F

EXT_WAKE

Wake up Indication

Power Good

Power Supplies

ALL SUPPLIES MUST BE POWERED

See Processor — Operating Conditions on Page 25.

VDDEXT

PI/ O Power Supply

VDDINT

Internal Power Supply

VDDFLASH

Flash Memory Power Supply

GND

Ground for All Supplies

Table 11. Processor — Signal Descriptions (Continued)

Signal Name

Type Function

Driver

Type

ADSP-BF504 数据表(PDF) 22 Page - Analog Devices

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