ADSP-BF504 datasheet(61/80 Pages) AD

61 / 80 page

Preliminary Technical Data

Rev. PrC

Page 61 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

determining how much that signal is attenuated in the

selected channel with a 50 kHz signal (0 V to VREF). The result

obtained is the worst-case across all 12 channels for the ADC.

Intermodulation Distortion (IMD)

With inputs consisting of sine waves at two frequencies, fa

and fb, any active device with non-linearities create distortion

products at sum, and difference frequencies of mfa ± nfb

where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion

terms are those for which neither m nor n are equal to zero.

For example, the second-order terms include (fa + fb) and

(fa fb), while the third-order terms include (2fa + fb),

(2fa fb), (fa + 2fb), and (fa 2fb).

The ADC is tested using the CCIF standard where two input

frequencies near the top end of the input bandwidth are used.

In this case, the second-order terms are usually distanced in

frequency from the original sine waves, while the third-order

terms are usually at a frequency close to the input frequencies.

As a result, the second-order and third-order terms are speci-

fied separately. The calculation of the inter-modulation

distortion is as per the THD specification, where it is the ratio

of the rms sum of the individual distortion products to the

rms amplitude of the sum of the fundamentals expressed in

dBs.

Common-Mode Rejection Ratio (CMRR)

CMRR is defined as the ratio of the power in the ADC output

at full-scale frequency, f, to the power of a 100 mV p-p sine

wave applied to the common-mode voltage of VIN+ and VIN of

frequency fS as

CMRR (dB) = 10 log(Pf/PfS)

where:

Pf is the power at frequency f in the ADC output.

PfS is the power at frequency fS in the ADC output.

Power Supply Rejection Ratio (PSRR)

Variations in power supply affect the full-scale transition but

not the converter’s linearity. PSRR is the maximum change in

the full-scale transition point due to a change in power supply

voltage from the nominal value (see Figure 56 (PSRR vs. Sup-

ply Ripple Frequency Without Supply Decoupling).

Thermal Hysteresis

Thermal hysteresis is defined as the absolute maximum

change of reference output voltage after the device is cycled

through temperature from either

T_HYS+ = +25°C to TMAX to +25°C

T_HYS = +25°C to TMIN to +25°C

It is expressed in ppm by

where:

VREF (25°C) is VREF at 25°C.

VREF (T_HYS) is the maximum change of VREF at

T_HYS+ or T_HYS.

ADC — THEORY OF OPERATION

The following sections describe the ADC theory of operation.

Circuit Information

The ADC is a fast, micro-power, dual, 12-bit, single-supply,

ADC that operates from a 2.7 V to a 5.25 V supply. When oper-

ated from a 5 V supply, the ADC is capable of throughput rates

of up to 2 MSPS when provided with a 32 MHz clock, and a

throughput rate of up to 1.5 MSPS at 3 V.

The ADC contains two on-chip, differential track-and-hold

amplifiers, two successive approximation ADCs, and a serial

interface with two separate data output pins.

The serial clock input accesses data from the part but also pro-

vides the clock source for each successive approximation ADC.

The analog input range for the part can be selected to be a 0 V to

VREF input or a 2 × VREF input, configured with either single-

ended or differential analog inputs. The ADC has an on-chip

2.5 V reference that can be overdriven when an external refer-

ence is preferred. If the internal reference is to be used elsewhere

in a system, then the output needs to buffered first.

The ADC also features power-down options to allow power sav-

ing between conversions. The power-down feature is

implemented via the standard serial interface, as described in

the ADC — Modes of Operation section.

Converter Operation

The ADC has two successive approximation ADCs, each based

around two capacitive DACs. Figure 68 (ADC Acquisition

Phase) and Figure 69 (ADC Conversion Phase) show simplified

schematics of one of these ADCs in acquisition and conversion

phase, respectively. The ADC is comprised of control logic, a

SAR, and two capacitive DACs. In Figure 68 (ADC Acquisition

Phase) (the acquisition phase), SW3 is closed, SW1 and SW2 are

in Position A, the comparator is held in a balanced condition,

and the sampling capacitor arrays acquire the differential signal

on the input.

)

(

)

(

)

(

)

(

−

REF

HYS

ppm

Figure 68. ADC Acquisition Phase

CAPACITIVE

DAC

CAPACITIVE

DAC

CONTROL

LOGIC

COMPARATOR

SW3

SW1

SW2

VIN+

VIN–

VREF

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