ADSP-BF504 datasheet(23/80 Pages) AD

23 / 80 page

Preliminary Technical Data

Rev. PrC

Page 23 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

Table 12. ADC — Signal Descriptions (ADSP-BF506F Processor Only)

Signal Name

Type Function

DGND

Digital Ground. This is the ground reference point for all digital circuitry on the internal ADC. Both DGND

pins should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be

at the same potential and must not be more than 0.3 V apart, even on a transient basis.

REF SELECT

Internal/External Reference Selection. Logic input. If this pin is tied to DGND, the on-chip 2.5 V reference

is used as the reference source for both ADC A and ADC B. In addition, Pin DCAPA and Pin DCAPB must be

tied to decoupling capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be

supplied to the internal ADC through the DCAPA and/or DCAPB pins.

AVDD

Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the

internal ADC. The AVDD and DVDD voltages should ideally be at the same potential and must not be more

than 0.3 V apart, even on a transient basis. This supply should be decoupled to AGND.

DCAPA, DCAPB (VREF)

Decoupling Capacitor Pins. Decoupling capacitors (470 nF recommended) are connected to these pins

to decouple the reference buffer for each respective ADC. Provided the output is buffered, the on-chip

reference can be taken from these pins and applied externally to the rest of a system. The range of the

external reference is dependent on the analog input range selected.

AGND

Analog Ground. Ground reference point for all analog circuitry on the internal ADC. All analog input

signals and any external reference signal should be referred to this AGND voltage. All three of these

AGND pins should connect to the AGND plane of a system. The AGND and DGND voltages ideally should

be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

VA1 to VA6

Analog Inputs of ADC A. These may be programmed as six single-ended channels or three true differ-

ential analog input channel pairs. See Table 51 (Analog Input Type and Channel Selection).

VB1 to VB6

Analog Inputs of ADC B. These may be programmed as six single-ended channels or three true differ-

ential analog input channel pairs. See Table 51 (Analog Input Type and Channel Selection).

RANGE

Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the

analog input channels. If this pin is tied to a logic low, the analog input range is 0 V to VREF. If this pin is

tied to a logic high when CS goes low, the analog input range is 2 × VREF. For details, see Table 51 (Analog

Input Type and Channel Selection).

SGL/DIFF

Logic Input. This pin selects whether the analog inputs are configured as differential pairs or single

ended. A logic low selects differential operation while a logic high selects single-ended operation. For

details, see Table 51 (Analog Input Type and Channel Selection).

A0 to A2

Multiplexer Select. Logic inputs. These inputs are used to select the pair of channels to be simulta-

neously converted, such as Channel 1 of both ADC A and ADC B, Channel 2 of both ADC A and ADC B,

and so on. The pair of channels selected may be two single-ended channels or two differential pairs.

The logic states of these pins need to be set up prior to the acquisition time and subsequent falling

edge of CS to correctly set up the multiplexer for that conversion. For further details, see Table 51

(Analog Input Type and Channel Selection).

Chip Select. Active low logic input. This input provides the dual function of initiating conversions on

the internal ADC and framing the serial data transfer. When connecting CS to a processor signal that is

three-stated during reset and/or hibernate, adding a pull-up resistor may prove useful to avoid random

ADC operation.

ADSCLK

Serial Clock. Logic input. A serial clock input provides the ADSCLK for accessing the data from the

internal ADC. This clock is also used as the clock source for the conversion process.

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