ADSP-BF504 datasheet(18/80 Pages) AD

18 / 80 page

Rev. PrC

Page 18 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

Preliminary Technical Data

To use these emulators, the target board must include a header

that connects the processor’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, multiprocessor scan

chains, signal buffering, signal termination, and emulator pod

logic, see (EE-68) Analog Devices JTAG Emulation Technical

Reference on the Analog Devices website (www.analog.com)—

use site search on “EE-68.” This document is updated regularly

to keep pace with improvements to emulator support.

ADC AND ACM INTERFACE

This section describes the ADC and ACM interface. System

designers should also consult the ADSP-BF50x Blackfin Proces-

sor Hardware Reference for additional information.

The ADC control module (ACM) provides an interface that

synchronizes the controls between the processor and the inter-

nal analog-to-digital converter (ADC) module. The ACM is

available on the ADSP-BF504, ADSP-BF504F, and

ADSP-BF506F processors, and the ADC is available on the

ADSP-BF506F processor only. The analog-to-digital conver-

sions are initiated by the processor, based on external or

internal events.

The ACM allows for flexible scheduling of sampling instants

and provides precise sampling signals to the ADC.

The ACM synchronizes the ADC conversion process; generat-

ing the ADC controls, the ADC conversion start signal, and

other signals. The actual data acquisition from the ADC is done

by the SPORT peripherals.

The serial interface on the ADC allows the part to be directly

connected to the ADSP-BF504, ADSP-BF504F, and

ADSP-BF506F processors using serial interface protocols.

Figure 6 shows how to connect an external ADC to the ACM

and one of the two SPORTs on the ADSP-BF504 or

ADSP-BF504F processors.

The ADC is integrated into the ADSP-BF506F product. Figure 7

shows how to connect the internal ADC to the ACM and to one

of the two SPORTs on the ADSP-BF506F processor.

The ADSP-BF504, ADSP-BF504F, and ADSP-BF506F proces-

sors interface directly to the ADC without any glue logic

required. The availability of secondary receive registers on the

serial ports of the Blackfin processors means only one serial port

is necessary to read from both DOUT pins simultaneously.

Figure 7 (ADC (Internal), ACM, and SPORT Connections)

shows both DOUTA and DOUTB of the ADC connected to one of

the processor’s serial ports. The SPORTx Receive Configuration

1 register and SPORTx Receive Configuration 2 register should

be set up as outlined in Table 9 (The SPORTx Receive Configu-

ration 1 Register (SPORTx_RCR1)) and Table 10 (The SPORTx

Receive Configuration 2 Register (SPORTx_RCR2)).

Figure 6. ADC (External), ACM, and SPORT Connections

SPORTx

DRxSEC

DRxPRI

RCLKx

RFSx

ADC

(EXTERNAL)

DOUTB

DOUTA

ADSCLK

RANGE

SGL/

DIFF

A[2:0]

ACM

ACLK

ACM_RANGE

ACM_SGLDIFF

ACM_A[2:0]

ADSP-BF504 / ADSP-BF504F

SPORT

SELECT

MUX

Figure 7. ADC (Internal), ACM, and SPORT Connections

Table 9. The SPORTx Receive Configuration 1 Register

(SPORTx_RCR1)

Setting

Description

RCKFE = 1

Sample data with rising edge of RSCLK

LRFS = 1

Active low frame signal

RFSR = 1

Frame every word

IRFS = 0

External RFS used

RLSBIT = 0

Receive MSB first

RDTYPE = 00

Zero fill

IRCLK = 0

External receive clock

RSPEN = 1

Receive enabled

TFSR = RFSR = 1