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ADSP-BF504 数据表(PDF) 42 Page - Analog Devices

部件名 ADSP-BF504
功能描述  Blackfin Embedded Processor
PDF  80 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADSP-BF504 数据表(HTML) 42 Page - Analog Devices

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Rev. PrC
|
Page 42 of 80
|
January 2010
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
Serial Peripheral Interface (SPI) Port—Slave Timing
Table 33 and Figure 22 describe SPI port slave operations.
Table 33. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
V
DDEXT = 1.8 V
V
DDEXT = 2.5/3.3 V
Min
Max
Min
Max
Unit
Timing Requirements
tSPICHS
Serial Clock High Period
2 × tSCLK –1.5
2 × tSCLK –1.5
ns
tSPICLS
Serial Clock Low Period
2 × tSCLK –1.5
2 × tSCLK –1.5
ns
tSPICLK
Serial Clock Period
4 × tSCLK
4 × tSCLK
ns
tHDS
Last SCK Edge to SPISS Not Asserted
2 × tSCLK –1.5
2 × tSCLK –1.5
ns
tSPITDS
Sequential Transfer Delay
2 × tSCLK –1.5
2 × tSCLK –1.5
ns
tSDSCI
SPISS Assertion to First SCK Edge
2 × tSCLK –1.5
2 × tSCLK –1.5
ns
tSSPID
Data Input Valid to SCK Edge (Data Input Setup)
1.6
1.6
ns
tHSPID
SCK Sampling Edge to Data Input Invalid
1.6
1.6
ns
Switching Characteristics
tDSOE
SPISS Assertion to Data Out Active
0
12.0
0
12.0
ns
tDSDHI
SPISS Deassertion to Data High Impedance
0
8.5
0
8.5
ns
tDDSPID
SCK Edge to Data Out Valid (Data Out Delay)
10
10
ns
tHDSPID
SCK Edge to Data Out Invalid (Data Out Hold)
0
0
ns
Figure 22. Serial Peripheral Interface (SPI) Port—Slave Timing
tSPICHS
tSPICLS
tSPICLK
tHDS
tSPITDS
tSDSCI
tSPICLS
tSPICHS
tDSOE
tDDSPID
tDDSPID
tDSDHI
tHDSPID
MSB VALID
LSB VALID
MSB VALID
tSSPID
LSB
LSB
MSB
MSB
tDSDHI
tHDSPID
tDSOE
tHSPID
tSSPID
tDDSPID
LSB VALID
SPISS
(INPUT)
SCKx
(CPOL = 0)
(INPUT)
SCKx
(CPOL = 1)
(INPUT)
MISOx
(OUTPUT)
MOSIx
(INPUT)
MISOx
(OUTPUT)
MOSIx
(INPUT)
CPHA = 1
CPHA = 0
tHSPID



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