ADSP-BF504 datasheet(3/80 Pages) AD

3 / 80 page

Preliminary Technical Data

Rev. PrC

Page 3 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

GENERAL DESCRIPTION

The ADSP-BF50x processors are members of the Blackfin

® fam-

ily of products, incorporating the Analog Devices/Intel Micro

Signal Architecture (MSA). Blackfin processors combine a dual-

MAC state-of-the-art signal processing engine, the advantages

of a clean, orthogonal RISC-like microprocessor instruction set,

and single-instruction, multiple-data (SIMD) multimedia capa-

bilities into a single instruction-set architecture.

The ADSP-BF50x processors are completely code compatible

with other Blackfin processors. ADSP-BF50x processors offer

performance up to 400 MHz and reduced static power con-

sumption. Differences with respect to peripheral combinations

are shown in Table 1.

By integrating a rich set of industry-leading system peripherals

and memory, Blackfin processors are the platform of choice for

next-generation applications that require RISC-like program-

mability, multimedia support, and leading-edge signal

processing in one integrated package.

PORTABLE LOW-POWER ARCHITECTURE

Blackfin processors provide world-class power management

and performance. They are produced with a low-power and

low-voltage design methodology and feature on-chip dynamic

power management, which provides the ability to vary both the

voltage and frequency of operation to significantly lower overall

power consumption. This capability can result in a substantial

reduction in power consumption, compared with just varying

the frequency of operation. This allows longer battery life for

portable appliances.

SYSTEM INTEGRATION

The ADSP-BF50x processors are highly integrated system-on-a-

chip solutions for the next generation of embedded industrial,

instrumentation, and power/motion control applications. By

combining industry-standard interfaces with a high-perfor-

mance signal processing core, cost-effective applications can be

developed quickly, without the need for costly external compo-

nents. The system peripherals include a watchdog timer; two

32-bit up/down counters with rotary support; eight 32-bit tim-

ers/counters with PWM support; six pairs of three-phase 16-bit

center-based PWM units; two dual-channel, full-duplex syn-

chronous serial ports (SPORTs); two serial peripheral interface

(SPI) compatible ports; two UARTs with IrDA support; a paral-

lel peripheral interface (PPI); a removable storage interface

(RSI) controller; an internal ADC with 12 channels, 12 bits, up

to 2 MSPS, and ACM controller; a controller area network

(CAN) controller; a two-wire interface (TWI) controller; and an

internal 32M bit flash.

PROCESSOR PERIPHERALS

The ADSP-BF50x processors contain a rich set of peripherals

connected to the core via several high-bandwidth buses, provid-

ing flexibility in system configuration as well as excellent overall

system performance (see the block diagram on Page 1). These

Blackfin processors contain high-speed serial and parallel ports,

an interrupt controller for flexible management of interrupts

from the on-chip peripherals or external sources, and power

management control functions to tailor the performance and

power characteristics of the processor and system to many

application scenarios.

The SPORT, SPI, UART, PPI, and RSI peripherals are sup-

ported by a flexible DMA structure. There are also separate

memory DMA channels dedicated to data transfers between the

processor’s various memory spaces, including boot ROM and

internal 32M bit synchronous burst flash. Multiple on-chip

buses running at up to 100 MHz provide enough bandwidth to

keep the processor core running along with activity on all of the

on-chip and external peripherals.

The ADSP-BF50x processors include an interface to an off-chip

voltage regulator in support of the processor’s dynamic power

management capability.

Table 1. Processor Comparison

Feature

ADSP-

BF504

ADSP-

BF504F

ADSP-

BF506F

Up/Down/Rotary Counters

Timer/Counters with PWM

3-Phase PWM Units

SPORTs

SPIs

UARTs

Parallel Peripheral Interface

Removable Storage Interface

CAN

TWI

Internal 32M Bit Flash

–

ADC Control Module (ACM)

Internal ADC

–

GPIOs

L1 Instruction SRAM

16K

L1 Instruction SRAM/Cache

16K

L1 Data SRAM

16K

L1 Data SRAM/Cache

16K

L1 Scratchpad

L3 Boot ROM

Maximum Speed Grade1

1 Maximum speed grade is not available with every possible SCLK selection.

400 MHz

Maximum System Clock Speed

100 MHz

Package Options

88-Lead

LFCSP

88-Lead

LFCSP

120-Lead

LQFP

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