ADSP-BF504 datasheet(69/80 Pages) AD

69 / 80 page

Preliminary Technical Data

Rev. PrC

Page 69 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

Power-Up Times

As described in detail, the ADC has two power-down modes,

partial power-down and full power-down. This section deals

with the power-up time required when coming out of either of

these modes. It should be noted that the power-up times, as

explained in this section, apply with the recommended capaci-

tors in place on the DCAPA and DCAPB pins.

To power up from full power-down, approximately 1.5 ms

should be allowed from the falling edge of CS, shown as

tPOWER-UP2 in Figure 90 (Exiting Full Power-Down Mode). Pow-

ering up from partial power-down requires much less time. The

power-up time from partial power-down is typically 1 μs; how-

ever, if using the internal reference, then the ADC must be in

partial power-down for at least 67 μs in order for this power-up

time to apply.

When power supplies are first applied to the ADC, the ADC

may power up in either of the power-down modes or normal

mode. Because of this, it is best to allow a dummy cycle to elapse

to ensure the part is fully powered up before attempting a valid

conversion. Likewise, if it is intended to keep the part in the par-

tial power-down mode immediately after the supplies are

applied, then two dummy cycles must be initiated. The first

dummy cycle must hold CS low until after the 10th ADSCLK

falling edge (see Figure 86 (Normal Mode Operation)); in the

second cycle, CS must be brought high before the 10th ADSCLK

edge but after the second ADSCLK falling edge (see Figure 87

(Entering Partial Power-Down Mode)). Alternatively, if it is

intended to place the part in full power-down mode when the

supplies are applied, then three dummy cycles must be initiated.

The first dummy cycle must hold CS low until after the 10th

ADSCLK falling edge (see Figure 86 (Normal Mode Opera-

tion)); the second and third dummy cycles place the part in full

power-down (see Figure 89 (Entering Full Power-Down

Mode)).

Once supplies are applied to the ADC, enough time must be

allowed for any external reference to power up and charge the

various reference buffer decoupling capacitors to their final

values.

Power vs. Throughput Rate

The power consumption of the ADC varies with the throughput

rate. When using very slow throughput rates and as fast an

ADSCLK frequency as possible, the various power-down

options can be used to make significant power savings. How-

ever, the ADC quiescent current is low enough that even

without using the power-down options, there is a noticeable

variation in power consumption with sampling rate. This is true

whether a fixed ADSCLK value is used or if it is scaled with the

sampling rate. Figure 91 (Power vs. Throughput in Normal

Mode with VDD = 3 V) and Figure 92 (Power vs. Throughput

in Normal Mode with VDD = 5 V) show plots of power vs. the

throughput rate when operating in normal mode for a fixed

Figure 89. Entering Full Power-Down Mode

Figure 90. Exiting Full Power-Down Mode

THREE-STATE

110

ADSCLK

DOUTA

DOUTB

THREE-STATE

110

INVALID DATA

THE PART BEGINS

TO POWER UP.

THE PART ENTERS

PARTIAL POWER DOWN.

THE PART ENTERS

FULL POWER DOWN.

ADSCLK

DOUTA

DOUTB

INVALID DATA

VALID DATA

THE PART BEGINS

TO POWER UP.

THE PART IS FULLY POWERED UP,

SEE POWER-UP TIMES SECTION.

tPOWER-UP2

ADSP-BF504 数据表(PDF) 69 Page - Analog Devices

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