ADSP-BF504 datasheet(19/80 Pages) AD

19 / 80 page

Preliminary Technical Data

Rev. PrC

Page 19 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

NOTE:

The SPORT must be enabled with the following set-

tings: external clock, external frame sync, and active low frame

sync.

To implement the power-down modes, SLEN should be set to

1001 to issue an 8-bit SCLK burst. A Blackfin driver for the

ADC is available to download at www.analog.com.

INTERNAL ADC

An ADC is integrated into the ADSP-BF506F product. All ADC

signals are connected out to package pins to enable maximum

interconnect flexibility in mixed signal applications.

The internal ADC is a dual, 12-bit, high speed, low power, suc-

cessive approximation ADC that operates from a single 2.7 V to

5.25 V power supply and features throughput rates up to

2 MSPS. The device contains two ADCs, each preceded by a

3-channel multiplexer, and a low noise, wide bandwidth track-

and-hold amplifier that can handle input frequencies in excess

of 30 MHz.

Figure 8 shows the functional block diagram of the internal

ADC. The ADC features include:

• Dual 12-bit, 3-channel ADC

• Throughput rate: up to 2 MSPS

• Specified for DVDD and AVDD of 2.7 V to 5.25 V

• Pin-configurable analog inputs

• 12-channel single-ended inputs

• 6-channel fully differential inputs

• 6-channel pseudo differential inputs

• Accurate on-chip voltage reference: 2.5 V

• Dual conversion with read 437.5 ns, 32 MHz ADSCLK

• High speed serial interface

•SPI

®-/QSPITM-/MICROWIRETM-/DSP-compatible

•Low power shutdown mode

The conversion process and data acquisition use standard con-

trol inputs allowing easy interfacing to microprocessors or

DSPs. The input signal is sampled on the falling edge of CS; con-

version is also initiated at this point. The conversion time is

determined by the ADSCLK frequency. There are no pipelined

delays associated with the part.

The internal ADC uses advanced design techniques to achieve

very low power dissipation at high throughput rates. The part

also offers flexible power/ throughput rate management when

operating in normal mode as the quiescent current consump-

tion is so low.

The analog input range for the part can be selected to be a 0 V to

VREF (or 2 × VREF) range, with either straight binary or twos

complement output coding. The internal ADC has an on-chip

2.5 V reference that can be overdriven when an external refer-

ence is preferred.

Additional highlights of the internal ADC include:

• Two Complete ADC Functions Allow Simultaneous Sam-

pling and Conversion of Two Channels — Each ADC has

three fully/pseudo differential pairs, or six single-ended

channels, as programmed. The conversion result of both

channels is simultaneously available on separate data lines,

or in succession on one data line if only one serial connec-

tion is available.

• High Throughput with Low Power Consumption

• The internal ADC offers both a standard 0 V to VREF input

range and a 2 × VREF input range.

• No Pipeline Delay — The part features two standard suc-

cessive approximation ADCs with accurate control of the

sampling instant via a CS input and once off conversion

control.

Table 10. The SPORTx Receive Configuration 2 Register

(SPORTx_RCR2)

Setting

Description

RXSE = 1

Secondary side enabled

SLEN = 1111

16-bit data-word (or may be set to 1101 for

14-bit data-word)

Figure 8. ADC (Internal) Functional Block Diagram

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

DOUTA

OUTPUT

DRIVERS

CONTROL

LOGIC

T/H

BUF

VA1

VA2

VA3

VA4

VA5

VA6

MUX

REF

ADC

VDRIVE

REF SELECT

DCAPA

AVDD

DVDD

BUF

DOUTB

OUTPUT

DRIVERS

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

T/H

VB1

VB2

VB3

VB4

VB5

VB6

MUX

AGND AGND AGND DCAPB

DGND

ADSCLK

RANGE

SGL/DIFF

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