ADSP-BF504 datasheet(21/80 Pages) AD

21 / 80 page

Preliminary Technical Data

Rev. PrC

Page 21 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

SIGNAL DESCRIPTIONS

Signal definitions for the ADSP-BF50x processors are listed in

Table 11. All pins for the ADC (ADSP-BF506F processor only)

are listed in Table 12.

In order to maintain maximum function and reduce package

size and pin count, some pins have multiple, multiplexed func-

tions. In cases where pin function is reconfigurable, the default

state is shown in plain text, while the alternate functions are

shown in italics.

During and immediately after reset, all processor signals (not

ADC signals) are three-stated with the following exceptions:

EXT_WAKE is driven high and XTAL is driven in conjunction

with CLKIN to create a crystal oscillator circuit. During

hibernate, all signals are three-stated with the following excep-

tions: EXT_WAKE is driven low and XTAL is driven to a solid

logic level.

During and immediately after reset, all I/O pins have their input

buffers disabled until enabled by user software with the excep-

tion of the pins that need pull-ups or pull-downs, as noted in

Table 11.

Adding a parallel termination to CLKOUT may prove useful in

further enhancing signal integrity. Be sure to verify over-

shoot/undershoot and signal integrity specifications on actual

hardware.

Table 11. Processor — Signal Descriptions

Signal Name

Type Function

Driver

Type

Port F: GPIO and Multiplexed Peripherals

PF0/TSCLK0/UA0_RX/TMR6/CUD0

I/O GPIO/SPORT0 TX Serial CLK/UART0 RX/Timer6/Count Up Dir 0

TBD

PF1/RSCLK0/UA0_TX/TMR5/CDG0

I/O GPIO/SPORT0 RX Serial CLK/UART0 TX/Timer5/Count Down Dir 0

TBD

PF2/DT0PRI/PWM0_BH/PPI_D8/CZM0

I/O GPIO/SPORT0 TX Pri Data/PWM0 Drive B Hi/PPI Data 8/Counter Zero Marker 0

TBD

PF3/TFS0/PWM0_BL/PPI_D9/CDG0

I/O GPIO/SPORT0 TX Frame Sync/PWM0 Drive B Lo/PPI Data 9/Count Down Dir 0

TBD

PF4/RFS0/PWM0_CH/PPI_D10/TACLK0

I/O GPIO/SPORT0 RX Frame Sync/PWM0 Drive C Hi/PPI Data 10 /Alt Timer CLK 0

TBD

PF5/DR0PRI/PWM0_CL/PPI_D11/TACLK1

I/O GPIO/SPORT0 Pri RX Data/PWM0 Drive C Lo /PPI Data 11/Alt Timer CLK 1

TBD

PF6/UA1_TX/PWM0_TRIP/PPI_D12

I/O GPIO/UART1 TX/PWM0 TRIP/PPI Data 12

TBD

PF7/UA1_RX/PWM0_SYNC/PPI_D13/TACI3

I/O GPIO/UART1 RX/PWM0 SYNC/PPI Data 13/Alt Capture In 3

TBD

PF8/UA1_RTS/DT0SEC/PPI_D7

I/O GPIO/ UART1 RTS/ SPORT0 TX Sec Data/ PPI Data 7

TBD

PF9/UA1_CTS/DR0SEC/PPI_D6/CZM0

I/O GPIO/UART1 CTS/SPORT0 Sec RX Data/PPI Data 6/Counter Zero Marker 0

TBD

PF10/SPI0_SCK/TMR2/PPI_D5

I/O GPIO/SPI0 SCK/Timer2/PPI Data 5

TBD

PF11/SPI0_MISO/PWM0_TRIP/PPI_D4/TACLK2

I/O GPIO/ SPI0 MISO/ PWM0 TRIP / PPI Data 4 / Alt Timer CLK 2

TBD

PF12/SPI0_MOSI/PWM0_SYNC/PPI_D3

I/O GPIO/ SPI0 MOSI / PWM0 SYNC/ PPI Data 3

TBD

PF13/SPI0_SEL1/TMR3/PPI_D2/SPI0_SS

I/O GPIO/ SPI0 Slave Select 1 / Timer3 / PPI Data 2/ SPI0 Slave Select In

TBD

PF14/SPI0_SEL2/PWM0_AH/PPI_D1

I/O GPIO/ SPI0 Slave Select 2 / PWM0 AH / PPI Data 1

TBD

PF15/SPI0_SEL3/PWM0_AL/PPI_D0

I/O GPIO/ SPI0 Slave Select 3 / PWM0 AL /PPI Data 0

TBD

Port G: GPIO and Multiplexed Peripherals

PG0/SPI1_SEL3/TMRCLK/PPI_CLK/UA1_RX/TACI4 I/O GPIO/ SPI1 Slave Select 3 / Timer CLK/ PPI Clock/ UART1 RX / Alt Capture In 4

TBD

PG1/SPI1_SEL2/PPI_FS3/CAN_RX/TACI5

I/O GPIO/ SPI1 Slave Select 2 / PPI FS3 / CAN RX/ Alt Capture In 5

TBD

PG2/SPI1_SEL1/TMR4/CAN_TX/SPI1_SS

I/O GPIO/ SPI1 Slave Select 1 / Timer4 / CAN TX /SPI1 Slave Select In

TBD

PG3/HWAIT/SPI1_SCK/DT1SEC/UA1_TX

I/O GPIO/ HWAIT/ SPI1 SCK/SPORT1 TX Sec Data/ UART1 TX

TBD

PG4/SPI1_MOSI/DR1SEC/PWM1_SYNC/TACLK6

I/O GPIO/ SPI1 MOSI / SPORT1 Sec RX Data/ PWM1 SYNC /Alt Timer CLK 6

TBD

PG5/SPI1_MISO/TMR7/PWM1_TRIP

I/O GPIO/SPI1 MISO/Timer7 /PWM1 TRIP

TBD

PG6/ACM_SGLDIFF/SD_D3/PWM1_AH

I/O GPIO/ADC CM SGL DIFF /SD Data 3/PWM1 Drive A Hi

TBD

PG7/ACM_RANGE/SD_D2/PWM1_AL

I/O GPIO/ ADC CM RANGE/ SD Data 2 / PWM1 Drive A Lo

TBD

PG8/DR1SEC/SD_D1/PWM1_BH

I/O GPIO/SPORT1 Sec RX Data/SD Data 1 /PWM1 Drive B Hi

TBD

PG9/DR1PRI/SD_D0/PWM1_BL

I/O GPIO/SPORT1 Pri RX Data/SD Data 0 /PWM1 Drive B Lo

TBD

PG10/RFS1/SD_CMD/PWM1_CH/TACI6

I/O GPIO /SPORT1 RX Frame Sync/SD CMD /PWM1 Drive C Hi/Alt Capture In 6

TBD

PG11/RSCLK1/SD_CLK/PWM1_CL/TACLK7

I/O GPIO/SPORT1 RX Serial CLK/SD CLK/PWM1 Drive C Lo/Alt Timer CLK 7

TBD

PG12/UA0_RX/SD_D4/PPI_D15/TACI2

I/O GPIO/UART0 RX/SD Data 4/PPI Data 15 /Alt Capture In 2

TBD

PG13/UA0_TX/SD_D5/PPI_D14/CZM1

I/O GPIO/UART0 TX/SD Data 5/PPI Data 14 /Counter Zero Marker 1

TBD

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