ADSP-BF504 datasheet(2/80 Pages) AD

2 / 80 page

Rev. PrC

Page 2 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

Preliminary Technical Data

TABLE OF CONTENTS

Features ................................................................. 1

Memory ................................................................ 1

Peripherals ............................................................. 1

Table Of Contents .................................................... 2

Revision History ...................................................... 2

General Description ................................................. 3

Portable Low-Power Architecture ............................. 3

System Integration ................................................ 3

Processor Peripherals ............................................. 3

Blackfin Processor Core .......................................... 4

Memory Architecture ............................................ 5

Flash Memory ...................................................... 9

DMA Controllers .................................................. 9

Watchdog Timer .................................................. 9

Timers ............................................................... 9

Up/Down Counters and Thumbwheel Interfaces ........ 10

3-phase PWM Units ............................................ 10

Serial Ports ........................................................ 10

Serial Peripheral Interface (SPI) Ports ...................... 11

UART Ports (UARTs) .......................................... 11

Parallel Peripheral Interface (PPI) ........................... 11

RSI Interface ...................................................... 12

Controller Area Network (CAN) Interface ................ 12

TWI Controller Interface ...................................... 13

Ports ................................................................ 13

Dynamic Power Management ................................ 13

ADSP-BF50x Voltage Regulation ............................ 15

Clock Signals ..................................................... 15

Booting Modes ................................................... 16

Instruction Set Description ................................... 17

Development Tools ............................................. 17

Designing an Emulator-Compatible

Processor Board (Target) ................................... 17

ADC and ACM Interface ....................................... 18

Internal ADC ..................................................... 19

ADC Application Hints ........................................ 20

Related Documents .............................................. 20

Signal Descriptions ................................................. 21

Processor — Specifications ....................................... 25

Processor — Operating Conditions .......................... 25

Processor — Electrical Characteristics ...................... 27

Processor — Absolute Maximum Ratings .................. 30

ESD Sensitivity ................................................... 30

Package Information ............................................ 30

Processor — Timing Specifications .......................... 31

Processor — Output Drive Currents ........................ 49

Processor — Test Conditions ................................. 50

Processor — Environmental Conditions ................... 52

Flash Program and Erase Times and Endurance Cycles .... 53

Flash – Absolute Maximum Ratings ............................ 53

ADC — Specifications ............................................. 54

ADC — Timing Specifications ................................ 56

ADC — Absolute Maximum Ratings ........................ 57

ADC — Typical Performance Characteristics ............. 57

ADC — Terminology ........................................... 60

ADC — Theory of Operation ................................. 61

ADC — Modes of Operation .................................. 67

ADC — Serial Interface ........................................ 70

120-Lead LQFP Lead assignment ............................... 72

88-Lead LFCSP Lead assignment ................................ 75

Outline Dimensions ................................................ 78

Surface Mount Design .......................................... 79

Ordering Guide ..................................................... 79

REVISION HISTORY

1/10—Rev. PrB to Rev. PrC

Numerous small corrections and additions to document.

Major changes/additions include:

Revised all timing diagrams for clarity/consistency in Processor

— Timing Specifications .......................................... 31

Updated specifications (reference PCN 09_0173) in the Clock

and Reset Timing section to accurately describe processor cold-

startup/reset timing ..................................................31

To view product/process change notifications (PCNs) related to

this data sheet revision, please visit the processor's product page

on the www.analog.com website and use the View PCN link.

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