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TNETA1575 数据表(PDF) 17 Page - Texas Instruments

部件名 TNETA1575
功能描述  ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES
PDF  45 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETA1575 数据表(HTML) 17 Page - Texas Instruments

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TNETA1575
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI-HOST AND COPROCESSOR INTERFACES
SDNS040C – MAY 1996 – REVISED JUNE 1998
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
control-memory interface (continued)
The SAR control-memory port is used to select both the external SRAM that stores the local-data structures
and state information for the TNETA1575 and an external device that can be used to provide an external
scheduler and other transmit data structures. The total control-memory address space consists of 128K
locations, with 64K locations dedicated to the TNETA1575 SRAM, and the remaining 64K dedicated to an
external device such as an external scheduler (see Figure 3).
Control SRAM
64K
× 32
CMSELLO = low, CMSELHI = high
External Device
64K
× 32
CMSELLO = high, CMSELHI = low
Figure 3. Control-Memory Address Space
Control memory select bit CMSELHI is used to select the upper 64K-address space. CMSELHI is active low
when the higher 64K addresses are selected, and inactive when the lower 64K addresses are selected. The
control-memory select bit CMSELLO is used to select the lower 64K-address space.
In addition, when the CMSELLO terminal is active low and the lower 64K addresses are selected, the user can
select between a single 64K
× 32 SRAM bank or two 32K × 32 SRAM banks. The two terminals CMSB1 and
CMSB2 are active low and allow the user to select between the two banks, as follows:
1.
CMSELLO is active low and CMA15 is low to select bank 1 (CMSB1 is enabled).
2.
CMSELLO is active low and CMA15 is high to select bank 2 (CMSB2 is enabled).
There are 16 control-memory address terminals that are used to address the various blocks of control memory.
Together with the two select terminal (CMSELLO and CMSELHI) and the two bank operating terminals, these
20 terminals provide for a total of 128K addressable-memory locations.
CONTROL-MEMORY
ADDRESS SPACE SELECTED
(HEXADECIMAL)
CMSELLO
CMSB1
CMSB2
CMSELHI
00000–07FFF
L
L
H
H
08000–0FFFF
L
H
L
H
10000–1FFFF
H
H
H
L



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