TNETA1575

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH PCI-HOST AND COPROCESSOR INTERFACES

SDNS040C – MAY 1996 – REVISED JUNE 1998

13

POST OFFICE BOX 655303

connecting the TNETA1575 to the UTOPIA bus (See Figure 1 and Note A)

Switch Port

or Other

PHY Layer

Devices

TNETA1575

PHY mode

ATMCLK1 (82)

ATMCLK2 (64)

RESCLK (66)

RESDATA7–RESDATA0 (72–75, 77–80)

TXData

TXClk

RESSOC (70)

TXSoc

RESEN (67)

TXEnb

RESCLAV (69)

TXFull/TXClav

RESPAR (71)

TXPrty

RESPERR (81)

SEGCLK (95)

RXClk

SEGDATA7–SEGDATA0 (84–87, 89–92)

RXData

SEGSOC (97)

RXSoc

SEGEN (96)

RXEnb

SEGCLAV (98)

RXEmpty/RXClav

SEGPAR (94)

RXPrty

VCC

PHY/ATM (83)

TNETA1585

PHY mode

RXCLK (24)

RXDATA7–RXDATA0 (10, 12–13, 15–18, 20)

RXSOC (21)

RXEMPTY/RXCLAV (22)

RXEN (23)

GND

CONFIG(9)

UTOPIA

Bus

TXData7–TXData0

TXSoc

TXEnb

TXFull/TXClav

NOTE A: Figures 1 and 2 show the interconnections needed to interface to a TNETA1585 device. If the TNETA1575 is operated without the

external scheduler device, then the lines going to the TNETA1585 are ignored, and everything remains as depicted above.

CLOCK (26)

Figure 1. UTOPIA Bus Connections In PHY Mode