TNETA1575

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH PCI-HOST AND COPROCESSOR INTERFACES

SDNS040C – MAY 1996 – REVISED JUNE 1998

16

POST OFFICE BOX 655303

local-bus interface

This interface allows access to the registers in two devices on the local bus. The TNETA1575 accepts a ready

signal from devices on the bus as a handshake. This accommodates slow devices, and also can be used to relax

timing constraints on the register interface for PHY-layer devices. The local bus is accessed exclusively via

PCI-bus transactions with TNETA1575 as the slave, with the exception of the local-bus interrupt signal. The

12-bit address of the local bus comprises the PCI-bus address lines (bits 13–2). These directly drive the

local-bus address bits (11–0). The signals in this interface are defined in the terminal-function table of this

document.

control-memory interface

Control memory contains the local data structures and state information used by the device to transmit and

receive data on a virtual connection (VC) or channel. The scheduler table, transmit active-packet counters,

free-buffer ring-pointer table, and TX/RX DMA state table are located in control memory. The scheduler table

contains 2,048 entries, consisting of one word each. The transmit active-packet counters contain the number

of packets that have been queued for transmit on each packet segmentation ring. The free-buffer ring-pointer

table contains the pointers to the receive free-buffer rings. There are 256 entries in the free-buffer ring-pointer

table (one entry for each free-buffer ring), and each entry consists of two words. The TX/RX DMA state table

contains 2,048 entries, one entry for each transmit-/receive-channel pair. Each entry consists of 16 words; eight

words for the transmit operation and eight words for the receive operation. The definitions and functional

description of the TNETA1575 data structures are discussed in detail in the

TNETA1575 Programmer’s

Reference Guide, literature number SDNU015.

These local data structures are located off the chip in external SRAM. The TNETA1575 is designed to operate

with 15-ns (or faster) asynchronous SRAM devices. The total SRAM requirement to support a full

implementation of control memory is approximately 37K

× 32. The device can operate with a control-memory

SRAM of size 32K

× 32. A system design with the 32K × 32 SRAM size only supports up to 1,792 TX/RX-channel

pairs. To support the entire range of 2,048 TX/RX-channel pairs, the TNETA1575 requires a SRAM

configuration of 64K

× 32.

The control-memory map for the TNETA1575 device follows:

control-memory map

MEMORY BLOCK

SIZE (IN 32-BIT WORDS)

CONTROL-MEMORY

ADDRESS (HEX)

PCI-OFFSET ADDRESS

(HEX)

Scheduler table

2,048

00000–007FF

00000–01FFC

Active packet counters

1,024

00800–00BFF

02000–02FFC

Reserved

512

00C00–00DFF

03000–037FC

Free-buffer ring pointer-table

512

00E00–00FFF

03800–03FFC

TX/RX DMA state table

32,768

01000–08FFF

04000–23FFC

DMA lookup table†

4,096

09000–09FFF

24000–27FFF

Local-bus device 1 (LBCS1)

4,096

0A000–0AFFF

28000–2BFFC

Local-bus device 2 (LBCS2)

4,096

0B000–0BFFF

2C000–2FFFC

Reserved

16,384

0C000–0FFFF

30000–3FFFC

Traffic coprocessor memory space

65,536

10000–1FFFF

40000–7FFFC

† The DMA lookup table is physically located on the chip and is not located off of the chip in the control memory.