TNETA1575

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH PCI-HOST AND COPROCESSOR INTERFACES

SDNS040C – MAY 1996 – REVISED JUNE 1998

2

POST OFFICE BOX 655303

PGC PACKAGE

(TOP VIEW)

CMSELHI

CMBS1

CMBS2

ATMCLK2

RESCLK

RESEN

RESCLAV

RESSOC

RESPAR

RESDATA7

RESDATA6

RESDATA5

RESDATA4

GND

RESDATA3

RESDATA2

RESDATA1

RESDATA0

RESPERR

ATMCLK1

PHY/ATM

SEGDATA7

SEGDATA6

SEGDATA5

SEGDATA4

GND

SEGDATA3

SEGDATA2

SEGDATA1

SEGDATA0

SEGPAR

SEGCLK

SEGEN

SEGSOC

SEGCLAV

LBCS1

TESTMODE

TRST

TCK

TMS

TDO

TDI

GND

HPSACK

HPSREQ

PSB1

PSB0

PINTA

PRST

PCLK

PGNT

GND

PREQ

PAD31

PAD30

CMDATA3

GND

CMDATA2

CMDATA1

CMDATA0

GND

LINTR

RCCX

TCCX

DAX

GND

COPFULL

LRESET

LBDATA0

LBDATA1

GND

LBDATA2

LBDATA3

LBDATA4

LBDATA5

LBDATA6

GND

LBDATA7

LBREADY

LBCS2

LBR/W

GND

LBAD0

LBAD1

LBAD2

LBAD3

LBAD4

GND

LBAD5

LBAD6

LBAD7

LBAD8

GND

LBAD9

LBAD10

LBAD11

PSB6

GND

PSB5

PSB4

PSB3

PSB2

GND

TXQUERDY

SBLENGTH

LBINTR

PAD0

61

63

65

67

69

71

73

75

77

79

81

83

85

87

89

91

93

95

97

99

101

103

105

107

109

111

113

115

117

119

239

237

235

233

231

229

227

225

223

221

219

217

215

213

211

209

207

205

203

201

199

197

195

193

191

189

187

185

183

181

description (continued)

The connection parameter cell-delay variation tolerance (CDVT) is not supported by the TNETA1575 scheduler

on CBR connections.

This data sheet provides information on the hardware specifications of the TNETA1575 device. The document

contains information on the device interfaces, timing diagrams, electrical characteristics, terminal and package

information, and an overview of the device operation. All the information on the TNETA1575 data structures,

configuration, and features is provided in the

TNETA1575 Programmer’s Reference Guide, literature number

SDNU015.