TNETA1575

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH PCI-HOST AND COPROCESSOR INTERFACES

SDNS040C – MAY 1996 – REVISED JUNE 1998

39

POST OFFICE BOX 655303

operating characteristics (see Note 10 and Figure 22)

local-bus interface – read operation

NO.

PARAMETER

MIN

MAX

UNIT

1

td(LBCS1)1

Delay time, LBR/W

↑ to LBCS1↓

57

67

ns

2

td(LBREADY)

Delay time, LBREADY

↓ to LBCS1↑

115

125

ns

NOTE 10: If LBREADY does not go low within eight PCI-clock cycles after LBCS1 goes active low, TNETA1575 latches in the data of the

LBDATA7–LBDATA0 bus and terminates the read operation.

PCLK

(input)

LBAD11–LBAD0

(output)

LBDATA7–LBDATA0

(input)

LBCS1

(output)

2

LBR/W

(output)

LBREADY

(input)

1

Figure 22. Local-Bus Interface – Read Operation