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TNETA1575 数据表(PDF) 1 Page - Texas Instruments |
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TNETA1575 数据表(HTML) 1 Page - Texas Instruments |
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1 / 45 page ![]() TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Supports Segmentation and Reassembly of AAL5 Packets in Accordance With ITU-T Specifications I.361 and I.363 (11/93 Update) D Integrated 32-Bit PCI Bus 2.1 (06/95) Interface for Transferring Packet Data to and From Host Memory D Provides Simultaneous Segmentation of up to 2048 Packets D Provides Simultaneous Reassembly of up to 2048 Packets D Provides Full VPI/VCI Support (12 VPI Bits and 16 VCI Bits) for Transmit and Receive Operations D Supports Constant-Bit-Rate (CBR) Traffic via High-Priority Mechanism or Local Static Scheduler Table D Backward Compatible With the TNETA1570 in 32-Bit PCI Mode D Provides Support for Available-Bit-Rate (ABR) Traffic via External Coprocessor Interface (COPI) D Provides Support for VBR-nrt Traffic via External COPI D Transmit-Channel Sleep Mode Prevents the SAR Polling Channels When No Packets Are Queued D High-Performance Features Include Use of Sideband Signals to Reduce Polling Across the PCI Bus D Host Accesses to the PHY-Layer Device Can Be Performed Indirectly via the TNETA1575 Local Peripheral Bus D Local Peripheral Bus Maps the PHY Device Into the TNETA1575 PCI-Bus Address Space D Supports Easy Access to AAL5 Trailer Information D Supports Buffer Scatter/Gather (Transmit and Receive Buffer Chaining) D Optional Early Segmentation of Packets, So Segmentation Begins Once a Transmit Buffer Is Filled, Instead of Waiting for the Entire Packet to Be Available in Host Memory D Calculates the HEC Byte for the Header of an Outgoing Cell D Checks the HEC Byte of an Incoming Cell D UTOPIA Level 1-Compliant Cell Interface D Internal 32-Cell Receive FIFO D Cell Interface Can Be Programmed to Operate as Either a Physical (PHY-Layer) Interface or as a SAR/Switch (ATM-Layer) Interface D Provides Reassembly Time Out for Incoming Packets D Provides an Internal Loopback Capability From Transmit to Receive D Supports Boundary Scan Through a Five-Wire JTAG Interface in Accordance With IEEE Std 1149.1-1990 (Includes IEEE Std 1149.1a-1993) description The TNETA1575 is an asynchronous transfer mode (ATM) segmentation and reassembly (SAR) device with a peripheral component interconnect (PCI)-bus interface and a coprocessor interface (COPI). The TNETA1575 continues the line of Texas Instruments (TI) ™ ATM SAR devices directed toward the classical LAN-to-ATM translation market segment. Features have been extended to include the COPI interface, which interfaces to an external scheduler with high-performance features to eliminate polling on the PCI bus. The TNETA1575 is designed for the emerging class of high-performance enterprise networking hubs that utilize ATM in the backplane, in addition to the traditional frame-/packet-based bus systems. Some of the features required for this application include: high level of virtual channel/virtual path support, support for isochronous services, early segmentation, and high-performance, 32-bit PCI-bus support. The feature set required by cell-operating enterprise hubs is different from the sets being offered by other SAR devices, which are directed primarily toward the adapter card market. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1998, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Thundercell and TI are trademarks of Texas Instruments Incorporated. |
类似零件编号 - TNETA1575 |
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类似说明 - TNETA1575 |
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