TNETA1575

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH PCI-HOST AND COPROCESSOR INTERFACES

SDNS040C – MAY 1996 – REVISED JUNE 1998

28

POST OFFICE BOX 655303

timing requirements (see Figure 10)

PCI sideband

NO.

MIN

MAX

UNIT

1

td(PAD)

Delay time, PCLK high to PAD31–PAD0 valid

2

11

ns

2

tsu(PSB2)

Setup time, PSB2 high before PCLK

↑

7

ns

2

tsu(PSB4)

Setup time, PSB4 high before PCLK

↑

7

ns

2

tsu(PSB6)

Setup time, PSB6 high before PCLK

↑

7

ns

3†

th(PSB2)

Hold time, PSB2 high after PCLK

↑

1

ns

3†

th(PSB4)

Hold time, PSB4 high after PCLK

↑

1

ns

3†

th(PSB6)

Hold time, PSB6 high after PCLK

↑

1

ns

† This 1-ns minimum hold time deviates from the 0-ns minimum hold time specified in PCI-Local Bus Specification (Revision 2.1).

PCLK

(input)

PAD31–PAD0

(I/O)

PFRAME

(I/O)

PREQ

(output)

Data1

Address

PGNT

(input)

Data2

Data3

Data4

PSB2, PSB4,

PSB6 (inputs)

PIRDY

(I/O)

PTRDY

(I/O)

PDEVSEL

(I/O)

1

3

2

Data Phase

Address

Phase

Figure 10. Master Write Operation and PCI Sideband (PSB2, PSB4,and PSB6 Signals) Timing