TNETA1575

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH PCI-HOST AND COPROCESSOR INTERFACES

SDNS040C – MAY 1996 – REVISED JUNE 1998

3

POST OFFICE BOX 655303

Terminal Functions

PCI-bus interface

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

PAD31–PAD0

119–121,

123–124,

126–127, 129,

133–134,

136–139,

141–142,

158–160, 162,

164–167,

171–173,

175–177,

179, 181

I/O

(3 state)

PCI address bus and data bus. PAD31–PAD0 are multiplexed on the same PCI terminals.

During the first phase of the address phase of a transaction, PAD31–PAD0 contain a 32-bit

physical address. This phase is the clock cycle when PFRAME is asserted.

During the data phase, PAD7–PAD0 contain the least-significant byte and PAD31–PAD24

contain the most-significant byte. Write data is stable when PIRDY is asserted. Read data is

stable when PTRDY is asserted. Data is transferred during those clock cycles when both

PIRDY and PTRDY are asserted.

PCBE3–PCBE0

130, 144,

156, 169

I/O

(3 state)

PCI-bus command and byte enable. PCBE3–PCBE0 lines are multiplexed on the same PCI

terminals. During the address phase of a transaction, PCBE3–PCBE0 lines define the bus

command. During the data phase, PCBE3–PCBE0 lines define which bytes are valid.

PCLK

114

I

(TTL)

PCI clock. PCLK provides timing for all transactions on the PCI interface.

PDEVSEL

149

I/O

(3 state)

PCI device select. When actively driven, PDEVSEL indicates that the address of the driving

device is decoded as the target of the current access. As an input, PDEVSEL indicates

whether any device on the bus is selected.

PFRAME

145

I/O

(3 state)

PCI frame. PFRAME is driven by the current master to indicate the beginning and duration of

an access. PFRAME is asserted at the beginning of the bus transaction and remains asserted

during data transfer. When PFRAME is deasserted, the transaction is in the final data phase.

PGNT

116

I

(TTL)

PCI-bus grant. PGNT indicates to the agent that the arbiter has granted access to the bus.

PGNT is a point-to-point signal and every master has its own.

PIDSEL

131

I

(TTL)

PCI initialization and device select. PIDSEL is used as a chip select during configuration read

and write transactions.

PINTA

112

O

(open

drain)

PCI interrupt. PINTA is an interrupt request from PCI SAR. PINTA indicates to the host that

a condition has occurred that may require attention. The TNETA1575 uses only a single

interrupt line.

PIRDY

147

I/O

(3 state)

PCI initiator ready. PIRDY indicates the initiating agent’s (bus master) ability to complete the

current data phase of the transaction. During a write, PIRDY indicates valid data on

PAD31–PAD0. During a read, PIRDY indicates the master is prepared to accept the data.

PIRDY is used with PTRDY. Wait cycles are inserted until both PIRDY and PTRDY are

asserted.

PPAR†

155

I/O

PCI parity. PPAR is even parity across PAD31–PAD0 and PCBE3–PCBE0. For data phases,

PPAR is valid one clock after either PIRDY is asserted on a write or PTRDY is asserted on

a read Once asserted PPAR remains valid until one clock after the completion of the current

PPAR†

155

(3 state)

a read. Once asserted, PPAR remains valid until one clock after the completion of the current

data phase. The master drives the PPAR for address- and write-data phases, and the target

drives PPAR for the read-data phase.

PPERR‡

152

I/O

(3 state)

PCI parity error. PPERR reports a data-parity error on all commands except special cycle. An

agent cannot report a PPERR until it has claimed the access by asserting PDEVSEL and

completed a data phase.

† If the host does not desire to implement parity in the system, terminal 155 is connected through a resistor to a valid logic level and the SERR

enable bit in the PCI command register is set to 0.

‡ If the host does not desire to implement parity in the system, terminal 152 is connected through a 1-M

Ω pullup resister and the SERR enable

bit in the PCI command register is set to 0.