TNETA1575

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH PCI-HOST AND COPROCESSOR INTERFACES

SDNS040C – MAY 1996 – REVISED JUNE 1998

40

POST OFFICE BOX 655303

operating characteristics (see Note 11 and Figure 23)

local-bus interface – write operation

NO.

PARAMETER

MIN

MAX

UNIT

1

td(LBCS1)1

Delay time, LBR/W

↓ to LBCS1↓

57

67

ns

2

td(LBCS1)2

Delay time, LBAD11–LBAD0 valid to LBCS1

↓

145

155

ns

3

td(LBCS1)3

Delay time, LBDATA7–LBDATA0 valid to LBCS1

↓

57

67

ns

4

td(LBAD)

Delay time, LBCS1

↑ to LBAD11–LBAD0 invalid

265

275

ns

NOTE 11: The LBCS1 is asserted low for eight PCI-clock cycles during a write operation to allow access to slow devices.

PCLK

(input)

LBR/W

(output)

LBAD11–LBAD0

(output)

LBDATA7–LBDATA0

(output)

LBCS1

(output)

3

1

2

4

Figure 23. Local-Bus Interface – Write Operation