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TNETA1575 数据表(PDF) 37 Page - Texas Instruments

部件名 TNETA1575
功能描述  ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES
PDF  45 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETA1575 数据表(HTML) 37 Page - Texas Instruments

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TNETA1575
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI-HOST AND COPROCESSOR INTERFACES
SDNS040C – MAY 1996 – REVISED JUNE 1998
37
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
timing requirements (see Note 8 and Figure 20)
UTOPIA interface
NO.
MIN
MAX
UNIT
1
tw(RESCLKH)
Pulse duration, RESCLK high
12
ns
2
tw(RESCLKL)
Pulse duration, RESCLK low
12
ns
3
tsu(RESSOC)
Setup time, RESSOC high before RESCLK
↑
10
ns
4
tsu(RESEN)
Setup time, RESEN low before RESCLK
↑
10
ns
5
tsu(RESDATA)
Setup time, RESDATA7–RESDATA0 valid before RESCLK
↑
10
ns
6
tsu(RESPAR)
Setup time, RESPAR valid before RESCLK
↑
10
ns
7
th(RESSOC)
Hold time, RESSOC high after RESCLK
↑
1
ns
8
th(RESEN)
Hold time, RESEN low after RESCLK
↑
1
ns
NOTE 8: All output signals are generated on the rising edge of RESCLK.
operating characteristics (see Note 8 and Figure 20)
UTOPIA interface
NO.
PARAMETER
MIN
MAX
UNIT
9
td(RESCLAV)
Delay time, RESCLK
↑ to RESCLAV↑
1
20
ns
10
td(RESPERR)1
Delay time, RESCLK
↑ to RESPERR↓
1
20
ns
11
td(RESPERR)2
Delay time, RESCLK
↑ to RESPERR↑
1
20
ns
NOTE 8. All output signals are generated on the rising edge of RESCLK.
RESDATA7–
RESDATA0
(input)
RESCLAV
(output)
RESCLK
(input)
1
2
RESSOC
(input)
9
7
RESEN
(input)
8
Byte 53
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
3
4
5
Parity
Error
No Parity Error
11
6
10
RESPAR
(input)
RESPERR
(output)
Figure 20. Reassembly-Cell Interface – PHY/ATM Low



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