TNETA1575 datasheet(8/45 Pages) TI1

8 / 45 page

TNETA1575

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH PCI-HOST AND COPROCESSOR INTERFACES

SDNS040C – MAY 1996 – REVISED JUNE 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions (Continued)

local-bus interface

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

LBAD11–

LBAD0

194–195, 197,

199–202, 204,

206–209

(CMOS)

Local-bus address. LBAD11–LBAD0 are driven by the TNETA1575 and are used to

address the peripheral attached to the local bus. Terminal 194 is the most significant

bit.

LBR/W

211

(CMOS)

Local-bus read/write. LBR/W is an active-low signal that indicates a write operation and

is driven by the TNETA1575. A read operation is indicated as active high.

LBCS1

(CMOS)

Local-bus chip select 1. LBCS1 is an active-low signal that is used to select an external

peripheral on the TNETA1575 local bus.

LBCS2

212

(CMOS)

Local-bus chip select. 2 LBCS2 is an active-low signal that is used to select an external

peripheral on the TNETA1575 local bus.

LBREADY

214

(TTL)

(with internal

pullup)

Local-bus ready. LBREADY is driven by a local-bus slave device. The TNETA1575 has

two modes of operation on this input terminal. The default mode causes the

TNETA1575 to complete the bus transaction after eight PCI-bus cycles, regardless of

LBREADY. Alternatively, the TNETA1575 can be placed in a mode using LBREADY.

This is a 3.3-V tolerant input signal. If it is driven by a 5-V signal, it must be connected

to an external voltage divider consisting of a 36-k

Ω down resistor and a 24-kΩ up

resistor to ensure that the input is not driven above 3.3 V.

LBINTR

183

(TTL)

(with internal

pullup)

Local-bus interrupt. LBINTR is an active-low interrupt that is generated and driven by

a local-bus device. This signal must be connected to an external 2.2-k

Ω pullup resistor

that is connected to a 3.3-V voltage source.

LBDATA7–

LBDATA0

215, 217–220,

222, 224–225

I/O

(TTL input /

CMOS output)

and

(with internal

pullup)

Local-bus data. LBDATA7–LBDATA0 are used to transfer data to and from a local-bus

slave device, and are driven by the TNETA1575 or a local-bus slave device. LBDATA7,

(terminal 215) is the most significant bit.

boundary-scan interface

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

TCK

103

(TTL)

Test clock. TCK clocks the test-access-port (TAP) operation.

TDI

106

(TTL)

Test data input. TDI shifts serial-test data and instructions into the device during TAP operation.

TDO

105

(TTL)

Test data output. TDO shifts serial-test data and instructions out of the device during TAP

operation.

TMS

104

(TTL)

Test-mode select. TMS controls the state of the TAP controller.

TRST

102

(TTL)

Test reset. TRST asynchronously forces the TAP controller to a known state. This terminal must

be tied low when the JTAG port is not being used.

test signal

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

TESTMODE

101

(TTL)

Test mode. TESTMODE is used for device testing. High is for test mode and low is for normal

operation.

TNETA1575 数据表(PDF) 8 Page - Texas Instruments

TNETA1575 数据表(HTML) 8 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

数据表下载

链接网址

TNETA1575 数据表(PDF) 8 Page - Texas Instruments

TNETA1575 数据表(HTML) 8 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

数据表 下载

链接网址

数据表下载