TNETA1575

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH PCI-HOST AND COPROCESSOR INTERFACES

SDNS040C – MAY 1996 – REVISED JUNE 1998

26

POST OFFICE BOX 655303

timing requirements (see Figure 8)

PCI-bus interface

NO.

MIN

MAX

UNIT

1

tsu(PIDSEL)

Setup time, PIDSEL high before PCLK

↑

7

ns

2

tsu(PAD)

Setup time, PAD31–PAD0 valid before PCLK

↑

7

ns

3

tsu(PFRAME)

Setup time, PFRAME low before PCLK

↑

7

ns

4

tsu(PIRDY)

Setup time, PIRDY low before PCLK

↑

7

ns

5†

th(PIDSEL)

Hold time, PIDSEL high after PCLK

↑

1

ns

6†

th(PIRDY)

Hold time, PIRDY low after PCLK

↑

1

ns

† This 1-ns minimum hold time deviates from the 0-ns minimum hold time specified in PCI-Local Bus Specification (Revision 2.1).

operating characteristics (see Figure 8)

PCI-bus interface

NO.

PARAMETER

MIN

MAX

UNIT

7

td(PTRDY)

Delay time, PCLK

↑ to PTRDY↓

2

11

ns

PCLK

(input)

PFRAME

(input)

PCBE3–

PCBE0

(input)

PIRDY

(input)

PTRDY

(output)

PDEVSEL

(output)

Data

Bus Cmd

BE

PIDSEL

(input)

1

5

PAD31–

PAD0

(I/O)

Address

Address Phase

2

3

4

7

6

Figure 8. Write Operation (PCI SAR as Slave)