TNETA1575

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH PCI-HOST AND COPROCESSOR INTERFACES

SDNS040C – MAY 1996 – REVISED JUNE 1998

11

POST OFFICE BOX 655303

As described in the PCI local-bus specification rev 2.1, the TNETA1575 provides a 64-byte configuration space

that can be accessed by system software for configuration, initialization, and error handling. The TNETA1575

responds to type 0 configuration accesses.

A configuration map of the 64-byte configuration space is as follows:

ADDRESS

BYTE 3

BYTE 2

BYTE 1

BYTE 0

READ/WRITE

0x00

Device ID

Vendor ID

R

0x04

Status

Command

R/W

0x08

Class Code

Revision ID

R

0x0C

BIST†

Header Type

Latency Timer

Cache Line Size

R/W

0x10

Base Address 0

R/W

0x14

Base Address 1†

R/W

0x18

Base Address 2†

R/W

0x1C

Base Address 3†

R/W

0x20

Base Address 4†

R/W

0x24

Base Address 5†

R/W

0x28

Cardbus CIS Pointer†

R

0x2C

Subsystem ID†

Subsystem Vendor ID†

R/W

0x30

Expansion ROM Base Address†

R/W

0x34

Reserved (returns 0 when read)

—

0x38

Reserved (returns 0 when read)

—

0x3C

Max_Lat

Min_Gnt

Interrupt Pin

Interrupt Line

R/W

0x40

Reserved

Reserved

Reserved

Reserved

R/W

0x44–0xFF

Reserved (returns 0 when read)

R

† Optional registers are not implemented for the TNETA1575, which return 0 when read.

The control memory is accessed via the host PCI interface in full 32-bit words. Byte enable is not supported.

All four bytes in a 32-bit word in the control memory are read or written in a single instruction.

If none of the byte enables are asserted for a write instruction, none of the data in the 32-bit word is altered. If

any byte enable is asserted, then the entire 32-bit word is overwritten.

cell interface

The TNETA1575 transfers and receives ATM cells through the cell interface. The cell interface is designed in

accordance with the ATM forum UTOPIA level 1 specification and is configurable as either an 8-bit PHY or ATM

interface. The ATM mode is chosen when the TNETA1575 interfaces with a framer such as the TNETA1500.

The PHY mode is chosen when the TNETA1575 interfaces with a switch port. The operation of this dual

ATM/PHY interface requires the use of two external terminals – ATMCLK and PHY/ATM. The ATMCLK output

is a buffered version of the PCI clock.

When PHY/ATM is high (PHY mode), the segmentation interface functions as a PHY-RX port and the

reassembly interface functions as a PHY-TX port. The clock speed supported by the interface is a maximum

of 33 MHz. In this mode, the ATMCLK output normally is not used by the cell interface.

When PHY/ATM is low (ATM mode), the segmentation interface functions as an ATM-TX port and the

reassembly interface functions as an ATM-RX port. The clock speed supported by the interface is a maximum

of 33 MHz. In this mode, the ATMCLK can be used as the clock source to provide for data

transfers/synchronization or another external-clock source(s) can be used.

The interface operates as a synchronous 8-bit (byte-wide) data path. The interface functions with both

octet-level and cell-level handshaking.