TNETA1575

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH PCI-HOST AND COPROCESSOR INTERFACES

SDNS040C – MAY 1996 – REVISED JUNE 1998

42

POST OFFICE BOX 655303

APPLICATIONS INFORMATION

system-level overview (continued)

The TNETA1575 has the following internal FIFO capabilities:

The TX FIFO holds four cells.

RX FIFO holds 32 cells.

The TNETA1585 is an ABR scheduler that conforms to the ATM-forum’s interoperability specifications. Other

than scheduling cells, the primary function is to handle the processing of resource management (RM) cells in

both the transmit and receive directions.

A system-level interconnect of the chip set, with associated systems, is shown in Figure 24.

TNETA1575

ThunderCELLt

TNETA1585

ThunderCELLt

Control

Memory

Parameter

Memory

TNETA1500

ThunderCELLt

Fiber/Copper

Transceiver

COPI

Interface

UTOPIA

Interface

Parameter

Memory

Interface

Control

Memory

Interface

PCI Bus

Interface

Host

Controller

PCI

Memory

Controller

Local

Bus

32-Bit

PCI

Figure 24. System-Level Chip Set (TNETA1575, TNETA1585, and TNETA1500)

† Vendors can develop their own second-tier schedulers, which conform to the coprocessor interface as defined in this data sheet, in advance of

the availability of the TNETA1585 device.