TNETA1575

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH PCI-HOST AND COPROCESSOR INTERFACES

SDNS040C – MAY 1996 – REVISED JUNE 1998

23

POST OFFICE BOX 655303

timing requirements (see Figure 5)

PCI-bus interface

NO.

MIN

MAX

UNIT

1

tw(PCLKH)

Pulse duration, PCLK high

12

ns

2

tw(PCLKL)

Pulse duration, PCLK low

12

ns

3

tsu(PGNT)

Setup time, PGNT low before PCLK

↑

10

ns

4

tsu(PAD)

Setup time, PAD31–PAD0 valid before PCLK

↑

7

ns

5

tsu(PTRDY)

Setup time, PTRDY low before PCLK

↑

7

ns

6

tsu(PDEVSEL)

Setup time, PDEVSEL low before PCLK

↑

7

ns

7

th(PAD)

Hold time, PAD31–PAD0 valid after PCLK

↑

0

ns

8

th(PTRDY)

Hold time, PTRDY low after PCLK

↑

0

ns

9†

th(PDEVSEL)

Hold time, PDEVSEL low after PCLK

↑

1

ns

† This 1-ns minimum hold time deviates from the 0-ns minimum hold time specified in PCI-Local Bus Specification (Revision 2.1).

operating characteristics (see Figure 5)

PCI-bus interface

NO.

PARAMETER

MIN

MAX

UNIT

10

td(PFRAME)

Delay time, PCLK

↑ to PFRAME↓

2

11

ns

11

td(PAD)

Delay time, PCLK

↑ to PAD31–PAD0 valid

2

11

ns

12

td(PCBE)

Delay time, PCLK

↑ to PCBE3–PCBE0 valid

2

11

ns

13

td(PIRDY)

Delay time, PCLK

↑ to PIRDY↓

2

11

ns

14

td(PREQ)

Delay time, PCLK

↑ to PREQ↓

2

12

ns

PCLK

(input)

PREQ

(output)

PGNT

(input)

PAD31–

PAD0

(I/O)

PFRAME

(output)

PCBE3–

PCBE0

(output)

PIRDY

(output)

PTRDY

(input)

PDEVSEL

(input)

4

Address

11

6

Bus Command

10

5

1

2

14

3

7

BE No. S-1

Data 1

Data 2

Data 3

BE No.S-2

Data 4

BE No.S-3

BE No. S-4

9

12

13

Data Phase

Address Phase

8

Figure 5. Read Operation (PCI SAR as Master)