TNETA1575

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH PCI-HOST AND COPROCESSOR INTERFACES

SDNS040C – MAY 1996 – REVISED JUNE 1998

18

POST OFFICE BOX 655303

traffic coprocessor interface

The TNETA1575 provides a traffic coprocessor interface (COPI) to add flexibility to the segmentation

scheduling algorithm. The COPI is implemented using the control-memory interface and three unidirectional

serial channels that transfer information from the TNETA1575 to the coprocessor and COPI-full indicator signal.

The TNETA1575 acts as an initiator of all transfers to and from the coprocessor.

The primary method of communication between the TNETA1575 and a coprocessor is via the control-memory

interface. It is intended that an external coprocessor be mapped into the control-memory space, starting at

address 10000 and extending to address 1FFFF. This equates to a total address space of 64K 32-bit words that

is reserved for use by the coprocessor.

The mapping of the coprocessor in control memory provides a means for the TNETA1575 to initialize the

coprocessor, to obtain information related to the scheduling of cells, and to obtain RM cell contents.

In this document, the three serial channels and the COPI-full indicator signal are described.

received cell-indication channel

A serial-bit interface allows the TNETA1575 to signal to the coprocessor that a cell has been received on a

particular DMA channel. This interface is necessary to avoid duplicating the hardware that is used to resolve

a VPI/VCI to a DMA channel. When a cell is received, the VPI/VCI value from the header is extracted and is

used as a key in a lookup algorithm. When the lookup is complete, the TNETA1575 sends a 13-bit frame to the

coprocessor, which is formatted as follows:

DMA NUMBER

GOOD/BAD CELL INDICATOR

FRAMING

(12–2)

(1)

(0)

The frame is transmitted to the coprocessor through the RCCX terminal, starting with bit 0. When a frame is not

actively being transmitted, the RCCX terminal is driven to a 0.

transmitted cell-indication channel

A single-bit interface allows the TNETA1575 to signal to the coprocessor that a cell will be transmitted on a

particular DMA channel. This interface is necessary to facilitate statistics processing in the coprocessor and to

aid in ATM-forum available-bit-rate (ABR) scheduling. As soon as the TNETA1575 determines that it has the

data to send a cell, it simultaneously sends an 18-bit frame to the coprocessor, which is formatted as follows:

DMA NUMBER

CLP INDICATOR

CELL TYPE

SCHEDULING

SOURCE

SEND

ACKNOWLEDGE

FRAMING

(17–7)

(6)

(5–3)

(2)

(1)

(0)

The frame is transmitted to the coprocessor through the TCCX terminal, starting with bit 0. When a frame is not

actively being transmitted, the TCCX terminal is driven to a 0.

data-availability channel

A single-bit interface allows the TNETA1575 to signal to the coprocessor when data is available or unavailable

on a particular channel. When the host writes to the transmit queue register to notify the TNETA1575 that a

packet has been queued, or if the TNETA1575 completes segmentation of the last packet on a particular DMA

channel, a 13-bit frame is sent to the coprocessor, which is formatted as follows:

DMA NUMBER

DATA AVAILABLE/UNAVAILABLE

FRAMING

(12–2)

(1)

(0)

The frame is transmitted to the coprocessor through the DAX terminal, starting with bit 0. When a frame is not

actively being transmitted, the DAX terminal is driven to a 0.