TNETA1575 datasheet(4/45 Pages) TI1

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TNETA1575

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH PCI-HOST AND COPROCESSOR INTERFACES

SDNS040C – MAY 1996 – REVISED JUNE 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions (Continued)

PCI-bus interface (continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

PREQ

118

(CMOS)

PCI request. PREQ indicates to the arbiter that this agent desires use of the bus. Every master has

its own PREQ.

PRST

113

(TTL)

PCI reset. PRST forces the PCI sequence of each device to a known state.

PSB1–PSB0

110–111

(CMOS)

PCI sideband. PSB1–PSB0 lines define the size of the transfer when the TNETA1575 is the bus

master. The definitions of these signals are as follows:

00: 4-byte transfer

01: 16-byte transfer (except for receive-completion ring)

10: Payload transfer

11: Transfer to receive-completion ring (20-byte transfer)

PSB1–PSB0 are synchronous to the address phase of the bus-master operations by the TNETA1575.

The sideband signals do not change upon a bus retry after disconnect.

PSB2

187

(TTL)

PCI sideband 2. PSB2 is an indication from the host to the SAR that the host has read an entry from

the receive-completion ring without an interrupt. The SAR uses this signal to increment the

receive-completion-ring entry counter. Pulse duration is for one clock cycle synchronous to the PCI

clock. This input terminal has an internal 100-

µA pulldown active terminator. This is a 3.3-V tolerant

input signal. If it is driven by a 5-V signal, it must be connected to an external voltage divider

consisting of a 36-k

Ω down resistor and a 24-kΩ up resistor to ensure that the input is not driven

above 3.3 V.

PSB3

189

(CMOS)

PCI sideband 3. PSB3 is an indication from the SAR to the host that the SAR is reading an entry from

sideband-controlled free-buffer ring 1.

PSB3 is synchronous to the address phase of bus-master operations by the SAR.

PSB3 does not change upon a bus retry after disconnect. Pulse duration is for one clock cycle

synchronous to the PCI-address phase.

PSB4

190

(TTL)

PCI sideband 4. PSB4 is an indication from the host to the SAR that the host has written a new entry

into sideband-controlled free-buffer ring 1.

The SAR uses this signal to increment the sideband-controlled free-buffer ring-1 entry counter. Pulse

duration is for one clock cycle synchronous to the PCI clock. This input terminal has an internal

100-

µA pulldown active terminator. This is a 3.3-V tolerant input signal. If it is driven by a 5-V signal,

it must be connected to an external voltage divider consisting of a 36-k

Ω down resistor and a 24-kΩ

up resistor to ensure that the input is not driven above 3.3 V.

PSB5

191

(CMOS)

PCI sideband 5. PSB5 is an indication from the SAR to the host that the SAR is reading an entry from

sideband-controlled free-buffer ring 2.

PSB5 is synchronous to the address phase of bus-master operations by the SAR.

PSB5 does not change upon a bus retry after disconnect. Pulse duration is for one clock cycle

synchronous to the PCI-address phase.

PSB6

193

(TTL)

PCI sideband 6. PSB6 is an indication from the host to the SAR that the host has written a new entry

into sideband-controlled free-buffer ring 2. The SAR uses this signal to increment the

sideband-controlled free-buffer ring-2 entry counter. Pulse duration is for one clock cycle

synchronous to the PCI clock. This input terminal has an internal 100-

µA pulldown active terminator.

This is a 3.3-V tolerant input signal. If it is driven by a 5-V signal, it must be connected to an external

voltage divider consisting of a 36-k

Ω down resistor and a 24-kΩ up resistor to ensure that the input

is not driven above 3.3 V.

PSERR

154

I/O

(open

drain)

PCI system error. PSERR reports address-parity errors and data-parity errors on special-cycle

commands.

PSTOP

150

I/O

(3 state)

PCI stop. PSTOP indicates that the current target is requesting the master to stop the current

transaction.

PTRDY

148

I/O

(3 state)

PCI target ready. PTRDY indicates the target agent’s (selected device) ability to complete the current

data phase of the transaction. During a read, PTRDY indicates that valid data is present on

PAD31–PAD0. During a write, PTRDY indicates that the target is prepared to accept data.

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