TNETA1575

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH PCI-HOST AND COPROCESSOR INTERFACES

SDNS040C – MAY 1996 – REVISED JUNE 1998

24

POST OFFICE BOX 655303

timing requirements (see Figure 6)

PCI-bus interface

NO.

MIN

MAX

UNIT

1

tsu(PGNT)

Setup time, PGNT low before PCLK

↑

10

ns

2

tsu(PTRDY)

Setup time, PTRDY low before PCLK

↑

7

ns

3

tsu(PDEVSEL)

Setup time, PDEVSEL low before PCLK

↑

7

ns

4

th(PTRDY)

Hold time, PTRDY low after PCLK

↑

0

ns

5†

th(PDEVSEL)

Hold time, PDEVSEL low after PCLK

↑

1

ns

† This 1-ns minimum hold time deviates from the 0-ns minimum hold time specified in PCI-Local Bus Specification (Revision 2.1).

operating characteristics (see Figure 6)

PCI-bus interface

NO.

PARAMETER

MIN

MAX

UNIT

6

td(PREQ)

Delay time, PCLK

↑ to PREQ↓

2

12

ns

7

td(PFRAME)

Delay time, PCLK

↑ to PFRAME↓

2

11

ns

8

td(PCBE)

Delay time, PCLK

↑ to PCBE valid

2

11

ns

9

td(PIRDY)

Delay time, PCLK

↑ to PIRDY↓

2

11

ns

10

td(PAD)

Delay time, PCLK

↑ to PAD31–PAD0 valid

2

11

ns

11

td(PSB)

Delay time, PCLK

↑ to PSB1–PSB0 valid

2

11

ns

PCLK

(input)

PREQ

(output)

PGNT

(input)

PAD31–

PAD0

(output)

PFRAME

(output)

PCBE3–

PCBE0

(output)

PIRDY

(output)

PTRDY

(input)

PDEVSEL

(input)

6

1

10

7

8

9

2

3

Address

Bus Command

Data 1

Data 2

Data 4

BE No. S-1

BE No. S-2

BE No. S-3

Data 3

BE No. S-4

4

5

Data Phase

Address Phase

11

PSB1–PSB0

(output)

Figure 6. Write Operation (PCI SAR as Master)