TNETA1575 datasheet(32/45 Pages) TI1

部件名	TNETA1575

功能描述	ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES

PDF	45 Pages

Scroll/Zoom	100%

制造商	TI1 [Texas Instruments]

网页	http://www.ti.com

标志

32 / 45 page

TNETA1575

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH PCI-HOST AND COPROCESSOR INTERFACES

SDNS040C – MAY 1996 – REVISED JUNE 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

timing requirements (see Figure 14)

control-memory interface – read operation

NO.

MIN

MAX

UNIT

tsu(CMDATA)

Setup time, CMDATA31–CMDATA0 valid before PCLK

↑

th(CMDATA)

Hold time, CMDATA31–CMDATA0 valid after PCLK

↑

operating characteristics (see Figure 14)

control-memory interface read operation

NO.

PARAMETER

MIN

MAX

UNIT

td(CMAD)

Delay time, from PCLK

↑ to CMAD15–CMAD0 valid

td(CMOE)

Delay time, from PCLK

↑ to CMOE↓

CMAD15-

CMAD0

(output)

CMOE

(output)

CMWE

(output)

Valid

CMDATA31-

CMDATA0

(input)

Valid

PCLK

(input)

Figure 14. Control-Memory Interface – Read Operation

TNETA1575 数据表(PDF) 32 Page - Texas Instruments

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