TNETA1575 datasheet(7/45 Pages) TI1

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TNETA1575

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH PCI-HOST AND COPROCESSOR INTERFACES

SDNS040C – MAY 1996 – REVISED JUNE 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions (Continued)

control-memory interface

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

CMAD15–

CMAD0

58–57,

55–50, 48,

46–41, 39

(CMOS)

Control-memory address. CMAD15–CMAD0 contain a 16-bit physical address to the control

memory.

CMBS1

(CMOS)

Control memory bank select 1. CMBS1 selects bank 1, containing 32K

× 32 SRAM addresses

in the lower 64K addresses, when active low.

CMBS2

(CMOS)

Control memory bank select 2. CMBS2 selects bank 2, containing 32K

× 32 SRAM addresses

in the lower 64K addresses, when active low.

CMDATA31–

CMDATA0

35–33, 31–29,

27–25,

23–18, 16,

14–9, 7,

5–1, 240,

238–236

(TTL)

(CMOS)

Control-memory data. CMDATA31–CMDATA0 contain 32-bit data to/from the control memory.

CMOE

(CMOS)

Control-memory output enable. When CMOE is active low, the address is valid and data is read

on the rising edge of CMOE.

CMSELHI

(CMOS)

Control memory select high. CMSELHI selects the upper 64K control-memory addresses when

active low.

CMSELL0

(CMOS)

Control memory select low. CMSELL0 selects the lower 64K control-memory addresses when

active low.

CMWE

(CMOS)

Control-memory write enable. When CMWE is active low, the address and data are valid.

traffic coprocessor interface

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

RCCX

232

(CMOS)

Receive-cell status indication. RCCX indicates to the traffic coprocessor that a cell was

received on the UTOPIA interface, and the RX DMA channel was assigned to the cell.

TCCX

231

(CMOS)

Transmit-cell status indication. TCCX indicates to the traffic coprocessor that a cell was

transmitted from the SAR, and the TX DMA channel was assigned to the cell.

DAX

229

(CMOS)

Data availability indication. DAX indicates to the traffic coprocessor when data is available

on a particular channel or when the SAR has completed segmentation of a packet.

LRESET

226

(CMOS)

Local reset. LRESET provides a reset indication to the traffic coprocessor. LRESET is derived

from the PCI-bus reset input.

LINTR

233

(TTL)

Local interrupt. LINTR provides an interrupt indication from the traffic coprocessor to the

SAR. When LINTR goes active low, the SAR sets a bit in the status register and generates

a PCI interrupt unless the interrupt is masked through the interrupt mask register. This

terminal has an internal 100-

µA pullup active terminator. This signal must be connected to

an external 2.2-k

Ω pullup resistor that is connected to a 3.3-V voltage source.

COPFULL

227

(TTL)

Coprocessor full. COPFULL indicates that the traffic coprocessor RX FIFO is about to fill up.

A 100-

µA pulldown active terminator is connected to this input. The pulldown is disabled when

the COPPRES bit is set in the SAR configuration register.

TNETA1575 数据表(PDF) 7 Page - Texas Instruments

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TNETA1575 数据表(PDF) 7 Page - Texas Instruments

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