TNETX3100 datasheet(2/80 Pages) TI1

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TNETX3100

ThunderSWITCH™ 10-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS031D – JUNE 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

description (continued)

The TNETX3100 provides two 100-Mbit/s interfaces and eight 10-Mbit/s interfaces. Half-duplex ports support

collision-based flow control; the purpose of the flow control is to reduce the risk of data loss for a long burst of

activity. With full-duplex capability, ports 02–09 can support 20-Mbit/s connections and ports 00–01 can support

200-Mbit/s connections to desktops or high-speed servers. The uplink (port 00) also can interface to an external

routing engine. Besides the ten full-duplex ports, the TNETX3100 has three modes for making forwarding

decisions.

The desktop switch internally supports multiple MAC addresses per port (32 total addresses). If more than 32

addresses are required, an external address match (EAM) interface is supplied to support multiple addresses

per port. If an external routing engine is used, the uplink port supports frame tagging. The frame tagging provides

source port information to an external routing engine. For more flexibility, the TNETX3100 can support VLAN

for workgroup and segment-switching applications.

VLAN support is provided in two ways: 1) In the internal address mode, internal VLAN registers are used to

configure the destination ports for broadcast/multicast packets. 2) The EAM interface provides a hardware

mechanism to control broadcast/multicast packets based on the code provided on that interface. See

EAM

interface and VLAN support for more details.

Statistics for the Etherstat and remote monitoring (RMON) management information base are independently

collected for each of the ten ports. Access to the statistics counters is provided via the data input/output (DIO)

interface. The DIO interface is intended only for configuration and monitoring operations.

The TNETX3100 utilizes an extremely low-cost 60-ns memory solution extended data out (EDO) DRAM. The

packet memory has been implemented to effectively support both single-access operation and

page-burst-access operation. All DRAM buffer transfers are made within a page boundary, permitting fast-burst

accesses. A high-memory bandwidth is maintained, allowing all ports to be active without bottlenecking at the

memory buffer.

The TNETX3100 is fabricated with 3.3-V technology. The inputs are 5-V tolerant and the 3.3-V outputs can

directly interface to 5-V TTL-logic levels. This provides a broad choice of interfacing-device options.

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